Forums

ADCs in FPGAs

Started by Rick C August 30, 2020
I have looked at ADCs in FPGAs but never built one.  Obviously sigma delta is a good way to go as it can be done all digitally, or almost so.  I'm not completely clear on how to do it.  

Lattice has a reference design using an LVDS receiver as a comparator.  They use an RC filter on the output bit as the reference voltage for the input.  I'm having trouble relating this to the typical block diagram of the sigma delta converter.  Is this circuit the same thing?  

Anyone built one of these?  Is it practical to expect 12 bits of resolution with a 16 MHz clock rate and 1 kHz sample rate?  By 12 bits I mean a solid 12 bits of accuracy... the word width can be wider if that helps any. 

-- 

  Rick C.

  - Get 1,000 miles of free Supercharging
  - Tesla referral code - https://ts.la/richard11209
On 31/08/2020 02:57, Rick C wrote:
> I have looked at ADCs in FPGAs but never built one. Obviously sigma > delta is a good way to go as it can be done all digitally, or almost > so. I'm not completely clear on how to do it. > > Lattice has a reference design using an LVDS receiver as a > comparator. They use an RC filter on the output bit as the reference > voltage for the input. I'm having trouble relating this to the > typical block diagram of the sigma delta converter. Is this circuit > the same thing? > > Anyone built one of these? Is it practical to expect 12 bits of > resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12 > bits I mean a solid 12 bits of accuracy... the word width can be > wider if that helps any. >
I would not be confident at getting 12 bits accuracy inside a fast digital part - it's very difficult to have your supplies and references stable enough, and to avoid switching noise from the digital parts interfering with the analogue. A 1 kHz sample rate 14-bit ADC chip with SPI or I²C shouldn't cost much or take much space.
On 31/08/2020 01:57, Rick C wrote:
> I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. > > Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing? > > Anyone built one of these? Is it practical to expect 12 bits of resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a solid 12 bits of accuracy... the word width can be wider if that helps any. >
I've never tried - getting a decent ADC into a functioning FPGA seems like a very difficult task. Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4 will do you, it has programmable gain, multiplexer, choice of up to 8 channels, 15 ENOB etc. MK
On Monday, August 31, 2020 at 4:32:56 AM UTC-4, Michael Kellett wrote:
> On 31/08/2020 01:57, Rick C wrote: > > I have looked at ADCs in FPGAs but never built one. Obviously sigma de=
lta is a good way to go as it can be done all digitally, or almost so. I'm= not completely clear on how to do it.
> >=20 > > Lattice has a reference design using an LVDS receiver as a comparator. =
They use an RC filter on the output bit as the reference voltage for the i= nput. I'm having trouble relating this to the typical block diagram of the= sigma delta converter. Is this circuit the same thing?
> >=20 > > Anyone built one of these? Is it practical to expect 12 bits of resolu=
tion with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a s= olid 12 bits of accuracy... the word width can be wider if that helps any.
> >=20 > I've never tried - getting a decent ADC into a functioning FPGA seems=20 > like a very difficult task. > Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4=20 > will do you, it has programmable gain, multiplexer, choice of up to 8=20 > channels, 15 ENOB etc. >=20 > MK
Yes, I looked at that part. It's not as available as our target which is 1= 0,000 stocked... yes, that may sound unrealistic, but many devices meet tha= t requirement even if the FPGAs typically don't. Also it is a bit complica= ted to use. Configuring it from an FPGA is a bother... configuring it from= anything is a bother. lol But it certainly is an option. Very likely I = will include both options, internal ADC and external ADC. I'm not convince= d I can't get a decent 12 bit ADC using an LVDS I/O. The I/O banks have se= parate power and ground pins, so that reduces the switching currents. Also= , this is a very low power chip. It's not your city dimmer Virtex.=20 The irony is I wanted to go with a Gowin part because of the limited I/O co= unt and lack of LVDS on the iCE40 Ultra parts. Moving the ADC to a dedicat= ed chip frees up enough I/Os the iCE40 Ultra 39 I/O count works. Still nee= d a comparator or two for other functions that could be in the FPGA. I sup= pose I could justify the Gowin part in the 48QFN which still has LVDS for c= omparators. =20 I just got a call from Edge, a Gowin distributor. I guess they take seriou= sly inquiries of qty 10,000. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
> I have looked at ADCs in FPGAs but never built one. Obviously sigma delt=
a is a good way to go as it can be done all digitally, or almost so. I'm n= ot completely clear on how to do it. =20
>=20 > Lattice has a reference design using an LVDS receiver as a comparator. T=
hey use an RC filter on the output bit as the reference voltage for the inp= ut. I'm having trouble relating this to the typical block diagram of the s= igma delta converter. Is this circuit the same thing? =20
>=20
I'd say it is a delta modulator not a delta-sigma modulator
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
> mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C: > > I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. > > > > Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing? > > > > I'd say it is a delta modulator not a delta-sigma modulator
Sorry, I'm not clear on what distinction you are trying to make. First, what is "it"? -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
> On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote: > > mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C: > > > I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. > > > > > > Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing? > > > > > > > I'd say it is a delta modulator not a delta-sigma modulator > > Sorry, I'm not clear on what distinction you are trying to make. First, what is "it"? >
the commonly used "RC filter on the output bit used as reference voltage" I'd call a delta modulator in a delta-sigma input minus output is integrated and the reference voltage fixed
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:
> tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C: > > On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote: > > > mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C: > > > > I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I'm not completely clear on how to do it. > > > > > > > > Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I'm having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing? > > > > > > > > > > I'd say it is a delta modulator not a delta-sigma modulator > > > > Sorry, I'm not clear on what distinction you are trying to make. First, what is "it"? > > > > the commonly used "RC filter on the output bit used as reference voltage" I'd call a delta modulator > > in a delta-sigma input minus output is integrated and the reference voltage fixed
Ok, I understand what you mean now. That is what I was asking about. Thanks -- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.c=
om wrote:
> tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C: > > On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.c=
om wrote:
> > > mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C: > > > > I have looked at ADCs in FPGAs but never built one. Obviously sigm=
a delta is a good way to go as it can be done all digitally, or almost so. = I'm not completely clear on how to do it. =20
> > > >=20 > > > > Lattice has a reference design using an LVDS receiver as a comparat=
or. They use an RC filter on the output bit as the reference voltage for t= he input. I'm having trouble relating this to the typical block diagram of= the sigma delta converter. Is this circuit the same thing? =20
> > > >=20 > > >=20 > > > I'd say it is a delta modulator not a delta-sigma modulator > >=20 > > Sorry, I'm not clear on what distinction you are trying to make. First=
, what is "it"?=20
> >=20 >=20 > the commonly used "RC filter on the output bit used as reference voltage"=
I'd call a delta modulator
>=20 > in a delta-sigma input minus output is integrated and the reference volta=
ge fixed Here is my thinking. Some people talk about digital noise being the source= of noise limitations in this technique. The I/O bank on FPGAs are separat= e from the rest of the chip and each other. We have plenty of spare I/Os s= o we can dedicate a bank to ADC use. Then the I/Os for the ADC are not jus= t less noisy, but also it can be provided by it's own supply with lower noi= se and better accuracy... or more like tracking the 5 volt rail that powers= the sensors. =20 I've been mulling the distinction between delta-sigma (or sigma-delta, I ca= n never remember) and the delta modulator. A simple mod to the analog circ= uit should make it a delta-sigma. =20 Vref -----------------| Vin- | Vin ---RRR---o---o----| Vin+ | | | R --- | R --- | R | | | V | | | +--------| SD out This should provide the integration and quantization to be sigma-delta, rig= ht?=20 The part I'm not clear on is turning the bit stream into a number. I belie= ve the Lattice design simply counts the 1's on the comparator output. Does= that constitute a first order filter? =20 We can run this input at up to 33 MHz. At that rate we should have plenty = of samples to work with. Do you think we could potentially eke out a solid= 12 bits of performance with a sample rate of 1 kHz? =20 I've seen this discussed a lot, but never ran into anyone who has done it. = We now have four or five people on the electronic design part and things a= re moving so fast, I'm not sure there will be time to give this proper cons= ideration. Even though the motor, mechanicals and other parts are not desi= gned fully yet they want to push on the circuit board. =20 Someone said they had used an instantiated ADC in the Xilinx tools. Anyone= know if that is actually an ADC or if it is an ADC chip interface? =20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209
On 2020-10-23 Rick C wrote in comp.arch.fpga:
> > Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?
On what Xilinx device? At least the Zynq devices do have actual ADC's. -- Stef (remove caps, dashes and .invalid from e-mail address to reply by mail) I'm a fuschia bowling ball somewhere in Brittany