about the low power design

Can some have the material ahout the power design in fpga,and how to
estimate the power in fpga,as I know the flash based and antifuse based
fpga have the low power,but the design require reconfiguration.And have
some other reason,we must use the sram based fpga,cyclone  and spartan
3e has the low power,and I didn't konw how to estimate the power in the
project,and the power only I can use is in 300mw.Can someone give some
advice?

bjzhangwn wrote:

> Can some have the material ahout the power design in fpga,and how to
> estimate the power in fpga,as I know the flash based and antifuse based
> fpga have the low power,but the design require reconfiguration.And have
> some other reason,we must use the sram based fpga,cyclone  and spartan
> 3e has the low power,and I didn't konw how to estimate the power in the
> project,and the power only I can use is in 300mw.Can someone give some
> advice?

If power is the ultimate requirement, the you can
just lower the clock to fit the power source.

Datasheets and the free tools may also give some
information on power requirements. Some manufacturer
cheat by assuming only 10% or so of the cells to be
active.

Rene
-- 
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

bjzhangwn wrote:

> Can some have the material ahout the power design in fpga,and how to
> estimate the power in fpga,as I know the flash based and antifuse based
> fpga have the low power,but the design require reconfiguration.And have
> some other reason,we must use the sram based fpga,cyclone  and spartan
> 3e has the low power,and I didn't konw how to estimate the power in the
> project,and the power only I can use is in 300mw.Can someone give some
> advice?

Altera Quartus II (5.0 and up) - at least the non-free version - has fairly
accurate power estimation when given a representative simulation output
file.

300mW sounds doable in an EP1C3 or EP2C5 with high utlization and clock
speed.

Best regards,


Ben

The Spartan-3E Web Power tool can give you a first estimate.  It's
generally quite conservative and, as with all estimators, depends on
the quality of the information provided.

I'm assuming that your 300 mW power budget is for dynamic power
consumption.  Is this correct?  Your total power will be the quiescent
(standby) power + dynamic power consumption.

With dynamic power consumption, you have a few levers to control the
final result.  The two easier levers are input clock frequency and
voltage.  Lowering the input clock frequency directly lowers the
dynamic power.  Turn off functions when not using them, for example,
with a clock enable.  Power consumption goes up with the square of the
voltage, so using a lower voltage, if possible, provides an advantage.

The quiescent or standby number is always there but is more critical
for designs powered from a battery and wake up occasionally to perform
some function.  A question to also ask is wether for power consumption
reasons you want to consider absolute worst-case quiescent (i.e., all
devices are below this level) or typical case.  There can be
significant differences in battery lifetime.  The choice may be driven
by the system design requirements.  In extreme cases, you can even turn
off power to the FPGA, essentially creating a "Hibernate" mode.
---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.

Here's an important missing item from my previous post!

Xilinx Spartan-3E Web Power Tool Version 8.1.01
http://www.xilinx.com/cgi-bin/power_tool/power_Spartan3e

Thanks,300mw is the total power,include the quiescent and the dynamic
powers,and the prequncy I use is not high,about 20Mhz,The LUTs I use
are about 5k for look up table,2k registers.I want to know if I can
make it work under 300mvw.

Hi,

For power estimation, Altera provides two tools.  The most accurate
estimates are obtained from the Quartus II Power Play Power Analyzer
(as mentioned by Ben), especially if you provide simulation vectors.
We also have an Early Power Estimator spreadsheet that can be used for
estimates pre-HDL; once you have a design, you're better off estimating
the power in Quartus.

As of Quartus II 5.1, Quartus will perform push-button dynamic power
optimization.  It does this by reducing the capacitance of highly
toggling nets in your design, and by restructuring RAM and other logic.
 Results vary depending the type of design, how tight your timing
constraints are (the tool will do its best to continue to meet timing),
the power optimization effort level you set, and the availability of
simulation vectors (you don't need them thought to get some benefit).
For designs with some timing margin and simulation vectors, we see on
average 25% reduction in dynamic power as compared to the same designs
compiled in earlier versions of Quartus II.

You can find some tips on optimizing the dynamic power of your design
and how to run Quartus to analyze and optimize your power at:
http://www.altera.com/literature/hb/qts/qts_qii51016.pdf

You can download the Early Power Estimator for Cyclone II at:
http://www.altera.com/support/devices/estimator/pow-powerplay.html

Altera's Power Analysis & Optimization capabilities are summarized at:
http://www.altera.com/products/software/products/quartus2/design/qts-power_analysis.html

And I wouldn't be doing my job if I didn't mention that Cyclone II has
lower static power, lower dynamic power, and lower I/O than any
competing device, so its certainly worth your time to check it out.

Regards,

Paul Leventis
Altera Corp.

Hi again,

You should easily fit under 300 mW.  For a Cyclone II 2C8, a quick
Altera Early Power Estimator calculation comes out at ~161 mW, at 85C
junction temperature and assuming worst-case static power.  Other
assumptions here:
   5000 LUTs, 2000 FFs toggling 25% of the time at 20 Mhz
   50 3.3V LVTTL inputs and outputs driving 10 pFs of external loading
25% of the time at 20 Mhz (100% enable rate)
   1.20V supply voltage
   85C junction temperature (depends on your cooling solution and
ambient temperature -- lower worst-case temperatures = better static
power)
   Worst-case silicon

It's also likely your design would fit in a EP2C5, which would come out
around ~125 mW.

Regards,

Paul Leventis
Altera Corp.

bjzhangwn wrote:
> Thanks,300mw is the total power,include the quiescent and the dynamic
> powers,and the prequncy I use is not high,about 20Mhz,The LUTs I use
> are about 5k for look up table,2k registers.I want to know if I can
> make it work under 300mvw.

Steve Knapp brought up an important point about static power.  You may
actually do better with one of the older series (Spartan 2e perhaps)
made
on 1.3 micron process.  Static power can be quite high in the 90 nm
process parts.  At your operating frequency almost any FPGA will work.

Good luck,
Gabor

Thanks for your reply,and I want to use spartan -3e ,because spartan-3e
have the lower cost than spartan3L.the the quiescent  power spartan 3e
is bigger than spartan3L,except this,I want to know if the dynamic
power is the same if I take the same project to each,I also want to
know what will effect the de dynamic power(include the design I use
and the chip architecture),Thansks!