How does the DCM phase shifting circuitry work? Xilinx Spartan 3

Essentially I need to know, for any given DCM configuration, how much
the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm
thinking that if I understand better how the PS part of the DCM circuit
works I can answer this for myself. I've got a case in with Xilinx but
either they're not understanding my question, or they're not sure how
to answer, or who knows. Any help would be greatly appreciated. Here's
the correspondence so far:

----------------------
Me:
I'm using some DCMs in dynamic phase-shift mode in a Spartan 3 and I'm
trying to understand how the granularity of each dynamic phase shift is
tied to the period of CLKIN. Does the phase shift feature use a fixed
tap delay? If so, the phase shift granularity would not be dependent on
the period of CLKIN. Also, after reading XAPP462 I surmised that the
longer the period of CLKIN (slower the CLKIN frequency) the less number
of effective phase shift steps. This seems counter-intuitive. Can you
help me to understand how the dynamic phase shifting is implemented in
the DCM?
-----------------
Xilinx:
Craig,
The DCM can always delay ~10ns.  When your clock period is slower than
~100Mhz (10ns period), you will not be able to phase shift the full360
degrees.  Additionally for slower frequencies, taps are combined as per
XAPP462, such that you may not have 256 tap changes, but will still
have 10ns of delay to work with. It's a little confusing, but the
circuitry basically does not allow the same resolution at slow speeds
as it does at high.
Hope this clears things up.
------------------
Me:
Thanks for your very quick response. I'm beginning to understand a
little better. The goal is for us to know, for any given DCM config,
how much dynamic phase shift occurs each time we nail PSINCDEC. For a
DCM that has a max shift of 10ns and 512 steps or taps, is it safe to
say that each tap is about 20ps? I understand that for slower CLKIN
frequencies the taps could be combined to give 40ps, 60ps, etc. per
step, and thus you'd have less than 255 steps in either direction. Is
there a way to tell if the DCM we're using is combining taps, and how
many taps per step? Thanks!
-------------------
Xilinx:
Craig,
There will never be 512 taps, there are max 256 and each is around
40ps.  The weight of each unit of increment will depend on the
frequency of clk in.  This is where XAPP462's equations come in.
Sounds like you got it from there.
------------------------
Me:
No not quite. The 512 taps/steps I got from equation 4 (pg 42), where
TCLKIN is less than 10 ns and the phase shift limits are +/-255.
However that's for fixed phase shifting. For variable phase shifting
there's 256 taps/steps when the shift limits are +/-128. Still, are you
sure there's only 256 taps in the delay line, since there's +/-255
steps available in fixed phase shifting?

Also, if CLKIN is 250MHz and I step PSINCDEC once, will the output
clock shift in phase by 40ps (or one tap delay)? What if CLKIN is
300MHz and I step once, will the output clock shift in phase by the
same 40ps, or some multiple? Here I'm still confused as to how each
unit of increment is tied to the frequency of CLKIN. Equation 9 (pg 45)
doesn't hold true.
--------------------

The DCM is covered well in the data sheets.

The Spartan3 DC & Switching data sheet specifies a tap resolution of 30 to 
60 ps.

The variable phase shift is different between Spartan3 and Spartan3E.  Since 
you're using Spartan3, the "older" style of variable phase shift is used: 
each PSINCDEC event is 1/256 of the CLKIN, not 1 tap delay.  The Spartan3 
Functional data sheet has 3 paragraphs on Variable Phase Shift mode that 
talks about the 1/256 increment.  What might not be clear is that there is a 
period after the PSINCDEC event before the next event can be applied, 
providing a fundamental limit to the speed of phase adjustment the system 
can attain.  Those details are also mentioned in the same paragraphs.

Each PSINCDEC event *might not* result in a tap change since ~40 ps 
corresponds to 10 ns.  Faster than ~100 MHz will have more than one event 
per tap change on average.  Slower than ~100 MHz (the DCM is good to 25 MHz) 
you get more than one tap changed per event on average.  The transition 
point is dependent on the actual tap delay.

Happy reading!


"Craig Yarbrough" <hyarbr01@harris.com> wrote in message 
news:1144185498.329325.55690@e56g2000cwe.googlegroups.com...
> Essentially I need to know, for any given DCM configuration, how much
> the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm
> thinking that if I understand better how the PS part of the DCM circuit
> works I can answer this for myself. I've got a case in with Xilinx but
> either they're not understanding my question, or they're not sure how
> to answer, or who knows. Any help would be greatly appreciated. Here's
> the correspondence so far:
>
> ----------------------
> Me:
> I'm using some DCMs in dynamic phase-shift mode in a Spartan 3 and I'm
> trying to understand how the granularity of each dynamic phase shift is
> tied to the period of CLKIN. Does the phase shift feature use a fixed
> tap delay? If so, the phase shift granularity would not be dependent on
> the period of CLKIN. Also, after reading XAPP462 I surmised that the
> longer the period of CLKIN (slower the CLKIN frequency) the less number
> of effective phase shift steps. This seems counter-intuitive. Can you
> help me to understand how the dynamic phase shifting is implemented in
> the DCM?
> -----------------
> Xilinx:
> Craig,
> The DCM can always delay ~10ns.  When your clock period is slower than
> ~100Mhz (10ns period), you will not be able to phase shift the full360
> degrees.  Additionally for slower frequencies, taps are combined as per
> XAPP462, such that you may not have 256 tap changes, but will still
> have 10ns of delay to work with. It's a little confusing, but the
> circuitry basically does not allow the same resolution at slow speeds
> as it does at high.
> Hope this clears things up.
> ------------------
> Me:
> Thanks for your very quick response. I'm beginning to understand a
> little better. The goal is for us to know, for any given DCM config,
> how much dynamic phase shift occurs each time we nail PSINCDEC. For a
> DCM that has a max shift of 10ns and 512 steps or taps, is it safe to
> say that each tap is about 20ps? I understand that for slower CLKIN
> frequencies the taps could be combined to give 40ps, 60ps, etc. per
> step, and thus you'd have less than 255 steps in either direction. Is
> there a way to tell if the DCM we're using is combining taps, and how
> many taps per step? Thanks!
> -------------------
> Xilinx:
> Craig,
> There will never be 512 taps, there are max 256 and each is around
> 40ps.  The weight of each unit of increment will depend on the
> frequency of clk in.  This is where XAPP462's equations come in.
> Sounds like you got it from there.
> ------------------------
> Me:
> No not quite. The 512 taps/steps I got from equation 4 (pg 42), where
> TCLKIN is less than 10 ns and the phase shift limits are +/-255.
> However that's for fixed phase shifting. For variable phase shifting
> there's 256 taps/steps when the shift limits are +/-128. Still, are you
> sure there's only 256 taps in the delay line, since there's +/-255
> steps available in fixed phase shifting?
>
> Also, if CLKIN is 250MHz and I step PSINCDEC once, will the output
> clock shift in phase by 40ps (or one tap delay)? What if CLKIN is
> 300MHz and I step once, will the output clock shift in phase by the
> same 40ps, or some multiple? Here I'm still confused as to how each
> unit of increment is tied to the frequency of CLKIN. Equation 9 (pg 45)
> doesn't hold true.
> --------------------
> 

Craig Yarbrough wrote:
> Essentially I need to know, for any given DCM configuration, how much
> the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm
> thinking that if I understand better how the PS part of the DCM circuit
> works I can answer this for myself. I've got a case in with Xilinx but
> either they're not understanding my question, or they're not sure how
> to answer, or who knows. Any help would be greatly appreciated. Here's
> the correspondence so far:

Peter A. can probably help.
  It sounds like you are looking for a simple controlled delay line, 
with predictable behaviour ?

  The DCM is a lot more than that: when you see signals like 'locked'
and PSDONE, and mention of negative delays, then there is more
'under the hood' than a simple delay line.

  Thus you are likely to see jitter, but ISTR Peter A. has mentioned
there are ways to 'dumb down' the DCM, to a simpler subset, but more 
predictable operation.

ie your challenge is likely to be (somehow) turning off the features
you do not need :)

-jg


> 
> ----------------------
> Me:
> I'm using some DCMs in dynamic phase-shift mode in a Spartan 3 and I'm
> trying to understand how the granularity of each dynamic phase shift is
> tied to the period of CLKIN. Does the phase shift feature use a fixed
> tap delay? If so, the phase shift granularity would not be dependent on
> the period of CLKIN. Also, after reading XAPP462 I surmised that the
> longer the period of CLKIN (slower the CLKIN frequency) the less number
> of effective phase shift steps. This seems counter-intuitive. Can you
> help me to understand how the dynamic phase shifting is implemented in
> the DCM?
> -----------------
> Xilinx:
> Craig,
> The DCM can always delay ~10ns.  When your clock period is slower than
> ~100Mhz (10ns period), you will not be able to phase shift the full360
> degrees.  Additionally for slower frequencies, taps are combined as per
> XAPP462, such that you may not have 256 tap changes, but will still
> have 10ns of delay to work with. It's a little confusing, but the
> circuitry basically does not allow the same resolution at slow speeds
> as it does at high.
> Hope this clears things up.
> ------------------
> Me:
> Thanks for your very quick response. I'm beginning to understand a
> little better. The goal is for us to know, for any given DCM config,
> how much dynamic phase shift occurs each time we nail PSINCDEC. For a
> DCM that has a max shift of 10ns and 512 steps or taps, is it safe to
> say that each tap is about 20ps? I understand that for slower CLKIN
> frequencies the taps could be combined to give 40ps, 60ps, etc. per
> step, and thus you'd have less than 255 steps in either direction. Is
> there a way to tell if the DCM we're using is combining taps, and how
> many taps per step? Thanks!
> -------------------
> Xilinx:
> Craig,
> There will never be 512 taps, there are max 256 and each is around
> 40ps.  The weight of each unit of increment will depend on the
> frequency of clk in.  This is where XAPP462's equations come in.
> Sounds like you got it from there.
> ------------------------
> Me:
> No not quite. The 512 taps/steps I got from equation 4 (pg 42), where
> TCLKIN is less than 10 ns and the phase shift limits are +/-255.
> However that's for fixed phase shifting. For variable phase shifting
> there's 256 taps/steps when the shift limits are +/-128. Still, are you
> sure there's only 256 taps in the delay line, since there's +/-255
> steps available in fixed phase shifting?
> 
> Also, if CLKIN is 250MHz and I step PSINCDEC once, will the output
> clock shift in phase by 40ps (or one tap delay)? What if CLKIN is
> 300MHz and I step once, will the output clock shift in phase by the
> same 40ps, or some multiple? Here I'm still confused as to how each
> unit of increment is tied to the frequency of CLKIN. Equation 9 (pg 45)
> doesn't hold true.
> --------------------
> 

Craig,

The delay line has many taps, but the phase shifter has only 256 
possible settings (from 0/256 to 255/256 of one period).

So, if you increment, or decrement, you will phase shift by 1/256 of a 
period, or by nothing at all (if 1/256 of a period is less than one tap 
of the physical delay line).

Take a "simple" case of 39.063 MHz (25.6 ns period):

1/256 of 25.6 ns = 100 ps

Each increment or decrement will phase shift by 100 ps (or the nearest 
tap granularity to the desired phase).

Austin

Craig Yarbrough wrote:

> Essentially I need to know, for any given DCM configuration, how much
> the DCM outputs will shift in phase for each time I nail PSINCDEC. I'm
> thinking that if I understand better how the PS part of the DCM circuit
> works I can answer this for myself. I've got a case in with Xilinx but
> either they're not understanding my question, or they're not sure how
> to answer, or who knows. Any help would be greatly appreciated. Here's
> the correspondence so far:
> 
> ----------------------
> Me:
> I'm using some DCMs in dynamic phase-shift mode in a Spartan 3 and I'm
> trying to understand how the granularity of each dynamic phase shift is
> tied to the period of CLKIN. Does the phase shift feature use a fixed
> tap delay? If so, the phase shift granularity would not be dependent on
> the period of CLKIN. Also, after reading XAPP462 I surmised that the
> longer the period of CLKIN (slower the CLKIN frequency) the less number
> of effective phase shift steps. This seems counter-intuitive. Can you
> help me to understand how the dynamic phase shifting is implemented in
> the DCM?
> -----------------
> Xilinx:
> Craig,
> The DCM can always delay ~10ns.  When your clock period is slower than
> ~100Mhz (10ns period), you will not be able to phase shift the full360
> degrees.  Additionally for slower frequencies, taps are combined as per
> XAPP462, such that you may not have 256 tap changes, but will still
> have 10ns of delay to work with. It's a little confusing, but the
> circuitry basically does not allow the same resolution at slow speeds
> as it does at high.
> Hope this clears things up.
> ------------------
> Me:
> Thanks for your very quick response. I'm beginning to understand a
> little better. The goal is for us to know, for any given DCM config,
> how much dynamic phase shift occurs each time we nail PSINCDEC. For a
> DCM that has a max shift of 10ns and 512 steps or taps, is it safe to
> say that each tap is about 20ps? I understand that for slower CLKIN
> frequencies the taps could be combined to give 40ps, 60ps, etc. per
> step, and thus you'd have less than 255 steps in either direction. Is
> there a way to tell if the DCM we're using is combining taps, and how
> many taps per step? Thanks!
> -------------------
> Xilinx:
> Craig,
> There will never be 512 taps, there are max 256 and each is around
> 40ps.  The weight of each unit of increment will depend on the
> frequency of clk in.  This is where XAPP462's equations come in.
> Sounds like you got it from there.
> ------------------------
> Me:
> No not quite. The 512 taps/steps I got from equation 4 (pg 42), where
> TCLKIN is less than 10 ns and the phase shift limits are +/-255.
> However that's for fixed phase shifting. For variable phase shifting
> there's 256 taps/steps when the shift limits are +/-128. Still, are you
> sure there's only 256 taps in the delay line, since there's +/-255
> steps available in fixed phase shifting?
> 
> Also, if CLKIN is 250MHz and I step PSINCDEC once, will the output
> clock shift in phase by 40ps (or one tap delay)? What if CLKIN is
> 300MHz and I step once, will the output clock shift in phase by the
> same 40ps, or some multiple? Here I'm still confused as to how each
> unit of increment is tied to the frequency of CLKIN. Equation 9 (pg 45)
> doesn't hold true.
> --------------------
> 

Thanks for the responses. That clears things up quite a bit. One
followup question, is the ratio of tap increment/decrement to the CLKIN
frequency fixed at DCM creation, or is it dynamic? If during normal
operation I increase CLKIN from 39.063MHz to 51.723MHz will the ratio
remain the same? Or will I see a proportionally larger phase shift with
the faster clock?

- Craig

Craig Yarbrough wrote:
> Thanks for the responses. That clears things up quite a bit. One
> followup question, is the ratio of tap increment/decrement to the CLKIN
> frequency fixed at DCM creation, or is it dynamic? If during normal
> operation I increase CLKIN from 39.063MHz to 51.723MHz will the ratio
> remain the same? Or will I see a proportionally larger phase shift with
> the faster clock?
>
> - Craig

For Spartan-3 FPGAs, the VARIABLE phase shift is _always_ a fraction
(1/256th) of the input clock period--the equivalent of about 1.4
degrees or pi/128 radians.  In Spartan-3 FPGAs, the DCM logic converts
this value to the appropriate number of tap delays, with each tap being
between 30 to 60 ps.

Assume a 166.667 MHz clock, which has a 6 ns clock period.  Each
PSINCDEC increment/decrement step is 6/265 ns = ~23 ps, less than a tap
delay.  The DCM control logic will decide wether or not to actually
shift when the shift value falls below the tap resolution.

Or, let's take your specific example.

If CLKIN is 39.063 MHz, then the clock period is ~26 ns.  Each PSINCDEC
value is 26/256 ns = ~102 ps.

If you changed the input clock to 51.723 MHz (please reset the DCM when
changing input frequencies please), then the clock period shrinks to
~19.33 ns.  Now each PSINCDEC value is 19.33/256 ns = ~75.5 ps.  On
Spartan-3, the size of the PSINCDEC value changes according to the
input clock frequency.  Spartan-3E FPGAs behave differently.

Did this sufficiently answer your question?

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.

Perfect Steve thanks. Thanks everyone!

- Craig

Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
> Craig Yarbrough wrote:
> 
>>Thanks for the responses. That clears things up quite a bit. One
>>followup question, is the ratio of tap increment/decrement to the CLKIN
>>frequency fixed at DCM creation, or is it dynamic? If during normal
>>operation I increase CLKIN from 39.063MHz to 51.723MHz will the ratio
>>remain the same? Or will I see a proportionally larger phase shift with
>>the faster clock?
>>
>>- Craig
> 
> 
> For Spartan-3 FPGAs, the VARIABLE phase shift is _always_ a fraction
> (1/256th) of the input clock period--the equivalent of about 1.4
> degrees or pi/128 radians.  In Spartan-3 FPGAs, the DCM logic converts
> this value to the appropriate number of tap delays, with each tap being
> between 30 to 60 ps.
> 
> Assume a 166.667 MHz clock, which has a 6 ns clock period.  Each
> PSINCDEC increment/decrement step is 6/265 ns = ~23 ps, less than a tap
> delay.  The DCM control logic will decide wether or not to actually
> shift when the shift value falls below the tap resolution.
> 
> Or, let's take your specific example.
> 
> If CLKIN is 39.063 MHz, then the clock period is ~26 ns.  Each PSINCDEC
> value is 26/256 ns = ~102 ps.
> 
> If you changed the input clock to 51.723 MHz (please reset the DCM when
> changing input frequencies please), then the clock period shrinks to
> ~19.33 ns.  Now each PSINCDEC value is 19.33/256 ns = ~75.5 ps.  On
> Spartan-3, the size of the PSINCDEC value changes according to the
> input clock frequency.  

Would it be correct to also add this ?
- Chooses the nearest physical [~40ns] tap, to the desired delay (N x 
102ps, or N x 75.5ps)
- Saturates at nom 10ns


>Spartan-3E FPGAs behave differently.

Whilst we are on this subject, to this detail,
can you give some info on how does Spartan 3E differ, and why ?

-jg

Craig,

Remains the same.

Austin

Craig Yarbrough wrote:

> Thanks for the responses. That clears things up quite a bit. One
> followup question, is the ratio of tap increment/decrement to the CLKIN
> frequency fixed at DCM creation, or is it dynamic? If during normal
> operation I increase CLKIN from 39.063MHz to 51.723MHz will the ratio
> remain the same? Or will I see a proportionally larger phase shift with
> the faster clock?
> 
> - Craig
> 

Jim,

Yes, nearest tap to actual value, and as for how Spartan stuff works, I 
have to defer to those engineers (as they did things differently).

Austin


Jim Granville wrote:

> Steve Knapp (Xilinx Spartan-3 Generation FPGAs) wrote:
> 
>> Craig Yarbrough wrote:
>>
>>> Thanks for the responses. That clears things up quite a bit. One
>>> followup question, is the ratio of tap increment/decrement to the CLKIN
>>> frequency fixed at DCM creation, or is it dynamic? If during normal
>>> operation I increase CLKIN from 39.063MHz to 51.723MHz will the ratio
>>> remain the same? Or will I see a proportionally larger phase shift with
>>> the faster clock?
>>>
>>> - Craig
>>
>>
>>
>> For Spartan-3 FPGAs, the VARIABLE phase shift is _always_ a fraction
>> (1/256th) of the input clock period--the equivalent of about 1.4
>> degrees or pi/128 radians.  In Spartan-3 FPGAs, the DCM logic converts
>> this value to the appropriate number of tap delays, with each tap being
>> between 30 to 60 ps.
>>
>> Assume a 166.667 MHz clock, which has a 6 ns clock period.  Each
>> PSINCDEC increment/decrement step is 6/265 ns = ~23 ps, less than a tap
>> delay.  The DCM control logic will decide wether or not to actually
>> shift when the shift value falls below the tap resolution.
>>
>> Or, let's take your specific example.
>>
>> If CLKIN is 39.063 MHz, then the clock period is ~26 ns.  Each PSINCDEC
>> value is 26/256 ns = ~102 ps.
>>
>> If you changed the input clock to 51.723 MHz (please reset the DCM when
>> changing input frequencies please), then the clock period shrinks to
>> ~19.33 ns.  Now each PSINCDEC value is 19.33/256 ns = ~75.5 ps.  On
>> Spartan-3, the size of the PSINCDEC value changes according to the
>> input clock frequency.  
> 
> 
> Would it be correct to also add this ?
> - Chooses the nearest physical [~40ns] tap, to the desired delay (N x 
> 102ps, or N x 75.5ps)
> - Saturates at nom 10ns
> 
> 
>> Spartan-3E FPGAs behave differently.
> 
> 
> Whilst we are on this subject, to this detail,
> can you give some info on how does Spartan 3E differ, and why ?
> 
> -jg
>