Forums

Gowin FPGA Oddities

Started by Rick C September 15, 2020
Gowin seems to have some nice configuration modes in their parts.  Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash.  They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot.  But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces.  

In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable.  Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left.  If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver!  They also don't make any of this clear from the documentation.  You have to read the pin list and figure out that various signals are missing.  Each package and even each part are different.  

It is a chore figuring this stuff out.  Many aspects of these devices are inconsistent.  

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  Rick C.

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On 15/09/2020 04:26, Rick C wrote:
> Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. >
I get the impression that GOWIN (somewhat like Lattice) are very much driven by what major customers want. In another place we had a design which gave the micro access to the FPGA's slave flash device. The micro could hold the FPGA inert, burn the SPI flash chip and then allow the FPGA to boot from it. I once did a JTAG driver for an Atmel ARM micro - not an experience I wish to repeat ! With a decent logic analyser you could probably reverse engineer the JTAG coding if you really had to - but 8 pin flash chips are so cheap it hardly seems worth the effort. MK
On 09/15/2020 05:26 AM, Rick C wrote:
> Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. >
Do they have a BSDL file describing the register chain?
On Tue, 15 Sep 2020 09:14:41 +0100
Michael Kellett <mk@mkesc.co.uk> wrote:

> I get the impression that GOWIN (somewhat like Lattice) are very much > driven by what major customers want.
Fair comment, but there are other ways to get info and support. If not now, then probably soon: synth_gowin - synthesis for Gowin FPGAs http://www.clifford.at/yosys/cmd_synth_gowin.html Project Apicula - Documentation of the Gowin FPGA bitstream format. Project Apicula uses a combination of fuzzing and parsing of the vendor data files to find the meaning of all the bits in the bitstream. https://github.com/YosysHQ/apicula Progress - Improvements for gowin support #1449 https://github.com/YosysHQ/yosys/pull/1449 Dev Board question: https://www.eevblog.com/forum/fpga/gowin-fpgas/ Rumor: GoWin FPGAs are essentially based on SiliconBlue iCE55 (previous generation of Lattice iCE40) fabric matrix, with IO Logic lifted from Mach and DSP Lifted from ECP. https://www.eevblog.com/forum/fpga/gowin-fpgas/ Jan Coombs --
On Tuesday, September 15, 2020 at 4:14:50 AM UTC-4, Michael Kellett wrote:
> On 15/09/2020 04:26, Rick C wrote: > > Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. > > > I get the impression that GOWIN (somewhat like Lattice) are very much > driven by what major customers want. > In another place we had a design which gave the micro access to the > FPGA's slave flash device. The micro could hold the FPGA inert, burn the > SPI flash chip and then allow the FPGA to boot from it. > I once did a JTAG driver for an Atmel ARM micro - not an experience I > wish to repeat ! > With a decent logic analyser you could probably reverse engineer the > JTAG coding if you really had to - but 8 pin flash chips are so cheap it > hardly seems worth the effort. > > MK
The flash chip has to be burned via a JTAG programmer connected to the FPGA. It would be nice to have the option of programming the FPGA and/or flash chip from the MCU in many applications. I need to look harder at the 100 pin QFP. That may be a better package for this project and others. It supports all the slave SPI pins. Here the oddity is they only bring out a single Mode pin allowing JTAG, Auto Boot and Slave SPI, no Master SPI mode. Very bizarre. I think the support engineer gets tired of my questions. The answer to my question about the auto boot configuration time was odd and I didn't understand it. While the data is transferred from flash to RAM internally, it is done is a serial like manner and depends on the clock rate selected. From what I'm being told the data transfer is in bytes, so 8x the clock rate in bps. The clock rate is selected in the programming software, so it must be in the bit stream. There seem to be a number of unexpected "oddities" about these parts. It may well be that some customer required a specific pin out in a given package and so this is now what is sold to everyone. I recall late last year when I contacted them they were essentially looking for "whale" customers which dictated when they brought out what chip in what package. I guess the whales also dictate which config modes are provided in a package. I am finding that the Compatibility Comparison guide is essential. If all your I/Os are the same voltage as the Vccx it's no big deal, but they switch up Vccx and Vccon between different die in the same package. So watch out if you want to have device size options! -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
On Tuesday, September 15, 2020 at 10:11:16 AM UTC-4, Johann Klammer wrote:
> On 09/15/2020 05:26 AM, Rick C wrote: > > Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. > > > Do they have a BSDL file describing the register chain?
I haven't looked. -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
On Tuesday, September 15, 2020 at 10:53:58 AM UTC-4, Jan Coombs wrote:
> On Tue, 15 Sep 2020 09:14:41 +0100 > Michael Kellett <mk@mkesc.co.uk> wrote: > > > I get the impression that GOWIN (somewhat like Lattice) are very much > > driven by what major customers want. > > Fair comment, but there are other ways to get info and support. If not > now, then probably soon: > > synth_gowin - synthesis for Gowin FPGAs > http://www.clifford.at/yosys/cmd_synth_gowin.html > > Project Apicula - Documentation of the Gowin FPGA bitstream format. > Project Apicula uses a combination of fuzzing and parsing of the vendor > data files to find the meaning of all the bits in the bitstream. > https://github.com/YosysHQ/apicula > > Progress - Improvements for gowin support #1449 > https://github.com/YosysHQ/yosys/pull/1449 > > Dev Board question: > https://www.eevblog.com/forum/fpga/gowin-fpgas/ > > Rumor: GoWin FPGAs are essentially based on SiliconBlue iCE55 (previous > generation of Lattice iCE40) fabric matrix, with IO Logic lifted from > Mach and DSP Lifted from ECP. > https://www.eevblog.com/forum/fpga/gowin-fpgas/
I'll read the links, but I don't think they are too literally based on the Lattice/IceBlue devices. The static power consumption is much higher if I'm understanding the data sheets. The iCE55 parts were well under 100 uA with a boost up to 100 uA in the iCE40 line once Lattice took them over (likely to ease production testing rather than actual silicon changes). The Gowin parts are in the mA range. But I do find their data sheets hard to read. Lots of slightly unfamiliar terminology which makes me uncertain what exactly they are measuring. Thanks for the links. -- Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
tirsdag den 15. september 2020 kl. 05.26.33 UTC+2 skrev Rick C:
> Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. >
just make MCU SPI slave ? JTAG shouldn't be too terrible to do, https://www.eevblog.com/forum/projects/(poll)-fpga-board-form-factor/?action=dlattach;attach=928670
On Tuesday, September 15, 2020 at 1:03:17 PM UTC-4, lasselangwad...@gmail.com wrote:
> tirsdag den 15. september 2020 kl. 05.26.33 UTC+2 skrev Rick C: > > Gowin seems to have some nice configuration modes in their parts. Of course they have an auto boot from internal flash and JTAG can be used to program either the RAM or the Flash. They also have master and slave SPI modes, a serial mode that daisy chains multiple FPGAs and a parallel bus mode along with a mode to try reading external flash and fall back to internal auto boot. But... they don't always make all of the mode control pins available and/or the pins needed for the various interfaces. > > > > In the QN88 package they leave out Mode2 so only the auto boot and the two SPI modes are selectable. Then they leave out the slave serial input pin so only auto boot, master SPI and JTAG are left. If you want to configure the part from an MCU you are stuck unless you want to emulate a JTAG driver! They also don't make any of this clear from the documentation. You have to read the pin list and figure out that various signals are missing. Each package and even each part are different. > > > > It is a chore figuring this stuff out. Many aspects of these devices are inconsistent. > > > > just make MCU SPI slave ? > > JTAG shouldn't be too terrible to do, https://www.eevblog.com/forum/projects/(poll)-fpga-board-form-factor/?action=dlattach;attach=928670
How does that work? The MCU can pump out addressed data at Mbps? That's a tough thing to do in general and if it has anything else to do - even tougher. I guess when programming the FPGA there isn't anything else for the MCU to do, so it just has to retrieve the appropriate data quickly enough to get it into the SPI hardware to ship out. I don't know how much time that gives. I haven't seen the interface spec before. It just seems so lame to have the many modes in the chip and then to toss them away for one or two I/Os which can be reclaimed after booting or even before if not used in the mode selected. -- Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209
tirsdag den 15. september 2020 kl. 21.29.32 UTC+2 skrev Rick C:
> On Tuesday, September 15, 2020 at 1:03:17 PM UTC-4, lasselangwad...@gmail=
.com wrote:
> > tirsdag den 15. september 2020 kl. 05.26.33 UTC+2 skrev Rick C: > > > Gowin seems to have some nice configuration modes in their parts. Of=
course they have an auto boot from internal flash and JTAG can be used to = program either the RAM or the Flash. They also have master and slave SPI m= odes, a serial mode that daisy chains multiple FPGAs and a parallel bus mod= e along with a mode to try reading external flash and fall back to internal= auto boot. But... they don't always make all of the mode control pins ava= ilable and/or the pins needed for the various interfaces. =20
> > >=20 > > > In the QN88 package they leave out Mode2 so only the auto boot and th=
e two SPI modes are selectable. Then they leave out the slave serial input= pin so only auto boot, master SPI and JTAG are left. If you want to confi= gure the part from an MCU you are stuck unless you want to emulate a JTAG d= river! They also don't make any of this clear from the documentation. You= have to read the pin list and figure out that various signals are missing.= Each package and even each part are different. =20
> > >=20 > > > It is a chore figuring this stuff out. Many aspects of these devices=
are inconsistent. =20
> > >=20 > >=20 > > just make MCU SPI slave ? > >=20 > > JTAG shouldn't be too terrible to do, https://www.eevblog.com/forum/pro=
jects/(poll)-fpga-board-form-factor/?action=3Ddlattach;attach=3D928670
>=20 > How does that work? The MCU can pump out addressed data at Mbps? That's=
a tough thing to do in general and if it has anything else to do - even to= ugher. I guess when programming the FPGA there isn't anything else for the= MCU to do, so it just has to retrieve the appropriate data quickly enough = to get it into the SPI hardware to ship out. I don't know how much time th= at gives. I haven't seen the interface spec before. =20
>=20
you can usually setup a DMA to do most of the work
> It just seems so lame to have the many modes in the chip and then to toss=
them away for one or two I/Os which can be reclaimed after booting or even= before if not used in the mode selected.=20
>=20
and why is the same pins not used for slave and master? (and serial)