Forums

FPGA sensitivities

Started by John Larkin September 25, 2020

I have a time-critical thing where the signal passes through an XC7A15
FPGA and does a fair lot of stuff inside. I measured delay vs some
voltages:

1.8 aux   no measurable DC effect
 
3.3 vccio no measurable DC effect

2.5 vccio ditto (key io's are LVDS in this bank)

+1 core   -10 ps per millivolt!

If I vary the trigger frequency, I can see the delay heterodyning
against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track
that down.

A spritz of freeze spray on the chip had practically no effect on
delay through the chip, on a scope at 100 ps/div.

I expected sensitivity to core voltage, so we'll make sure we have a
serious, analog-quality voltage regulator next rev.

The temperature thing surprised me. I was used to CMOS having a
serious positive delay TC. Maybe modern FPGAs have some sort of
temperature compensation designed in?

We also have a ZYNQ on this board that crashes the ARM core
erratically, especially when the chip is hot. It might crash in maybe
a half hour MTBF if the chip reports 55C internally; the FPGA part
keeps going. At powerup boot from an SD card, it will always configure
the PL FPGA side, but will then fail to run our application if the
chip is hot. We're playing with DRAM and CPU clock rates to see if
that has much effect.



On 2020-09-25 15:16, John Larkin wrote:
> > > I have a time-critical thing where the signal passes through an XC7A15 > FPGA and does a fair lot of stuff inside. I measured delay vs some > voltages: > > 1.8 aux no measurable DC effect > > 3.3 vccio no measurable DC effect > > 2.5 vccio ditto (key io's are LVDS in this bank) > > +1 core -10 ps per millivolt! > > If I vary the trigger frequency, I can see the delay heterodyning > against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track > that down. > > A spritz of freeze spray on the chip had practically no effect on > delay through the chip, on a scope at 100 ps/div. > > I expected sensitivity to core voltage, so we'll make sure we have a > serious, analog-quality voltage regulator next rev. > > The temperature thing surprised me. I was used to CMOS having a > serious positive delay TC. Maybe modern FPGAs have some sort of > temperature compensation designed in? > > We also have a ZYNQ on this board that crashes the ARM core > erratically, especially when the chip is hot. It might crash in maybe > a half hour MTBF if the chip reports 55C internally; the FPGA part > keeps going. At powerup boot from an SD card, it will always configure > the PL FPGA side, but will then fail to run our application if the > chip is hot. We're playing with DRAM and CPU clock rates to see if > that has much effect.
Yecch, good to know--keeping the drift down to 1 ps requires the 1V supply to be stable to 100 ppm total. I don't think I've ever needed to use four-wire sensing on a logic supply, but you're probably going to have to. Cheers Phil Hobbs -- Dr Philip C D Hobbs Principal Consultant ElectroOptical Innovations LLC / Hobbs ElectroOptics Optics, Electro-optics, Photonics, Analog Electronics Briarcliff Manor NY 10510 http://electrooptical.net http://hobbs-eo.com
On Fri, 25 Sep 2020 16:49:51 -0400, Phil Hobbs
<pcdhSpamMeSenseless@electrooptical.net> wrote:

>On 2020-09-25 15:16, John Larkin wrote: >> >> >> I have a time-critical thing where the signal passes through an XC7A15 >> FPGA and does a fair lot of stuff inside. I measured delay vs some >> voltages: >> >> 1.8 aux no measurable DC effect >> >> 3.3 vccio no measurable DC effect >> >> 2.5 vccio ditto (key io's are LVDS in this bank) >> >> +1 core -10 ps per millivolt! >> >> If I vary the trigger frequency, I can see the delay heterodyning >> against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track >> that down. >> >> A spritz of freeze spray on the chip had practically no effect on >> delay through the chip, on a scope at 100 ps/div. >> >> I expected sensitivity to core voltage, so we'll make sure we have a >> serious, analog-quality voltage regulator next rev. >> >> The temperature thing surprised me. I was used to CMOS having a >> serious positive delay TC. Maybe modern FPGAs have some sort of >> temperature compensation designed in? >> >> We also have a ZYNQ on this board that crashes the ARM core >> erratically, especially when the chip is hot. It might crash in maybe >> a half hour MTBF if the chip reports 55C internally; the FPGA part >> keeps going. At powerup boot from an SD card, it will always configure >> the PL FPGA side, but will then fail to run our application if the >> chip is hot. We're playing with DRAM and CPU clock rates to see if >> that has much effect. > >Yecch, good to know--keeping the drift down to 1 ps requires the 1V >supply to be stable to 100 ppm total. I don't think I've ever needed to >use four-wire sensing on a logic supply, but you're probably going to >have to. > >Cheers > >Phil Hobbs
I don't expect to keep the delay stable to 1 ps over temperature. Below 1 ps/oC would wipe the competition. I do want to get the jitter down into the single digits of ps RMS. I boogered the +1 volt (Zynq core) supply voltage up to 1.1 volts and the ARM crash thing went away. Or the crash temperature went way up. So we have a timing problem. My engineers are working from home but one is burning me a new SD card to try, with slower clocks in the ARM and DRAM. I'll pop over soon and pick it up. She lives in a tiny rent-controlled apartment above Dolores Park. Her next-door neighbor on that block is one of the richest people in the world.
On Friday, September 25, 2020 at 3:16:19 PM UTC-4, John Larkin wrote:
> I have a time-critical thing where the signal passes through an XC7A15 > FPGA and does a fair lot of stuff inside. I measured delay vs some > voltages: > > 1.8 aux no measurable DC effect > > 3.3 vccio no measurable DC effect > > 2.5 vccio ditto (key io's are LVDS in this bank) > > +1 core -10 ps per millivolt! > > If I vary the trigger frequency, I can see the delay heterodyning > against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track > that down. > > A spritz of freeze spray on the chip had practically no effect on > delay through the chip, on a scope at 100 ps/div.
You don't say how much the total delay is or what your circuitry is other than "a fair lot of stuff". I'm pretty sure the FPGA makers focus on minimizing worst case delay rather than making it more even with temperature. No one would have much use for that when push comes to shove. If it works, just barely, at high temperature, what is the point of maintaining a bare timing margin at lower temps rather than letting it speed up? It may well be that when going on and off chip the I/O delays make up the lion's share of the timing and they may not behave the same as the bulk since they are mostly about large structures.
> I expected sensitivity to core voltage, so we'll make sure we have a > serious, analog-quality voltage regulator next rev. > > The temperature thing surprised me. I was used to CMOS having a > serious positive delay TC. Maybe modern FPGAs have some sort of > temperature compensation designed in?
Hardly. More like they focus on optimizing clock speeds so raw on chip logic and routing speed. Try using a clock in your design and see how fast it will operate. We did that once when the design software was marginal and did not properly estimate delay on a heavily loaded net. It would report meeting the clock speed requirement when it was actually failing. Cold spray would make it work. In the end we had to test using a heat plate to be able to ship a product.
> We also have a ZYNQ on this board that crashes the ARM core > erratically, especially when the chip is hot. It might crash in maybe > a half hour MTBF if the chip reports 55C internally; the FPGA part > keeps going. At powerup boot from an SD card, it will always configure > the PL FPGA side, but will then fail to run our application if the > chip is hot. We're playing with DRAM and CPU clock rates to see if > that has much effect.
What a PITA. Timing/heat problems are awkward to debug when the tools are not of much help. Are you not cooling it enough to keep it from crashing? -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
On Fri, 25 Sep 2020 12:16:07 -0700, John Larkin
<jlarkin@highland_atwork_technology.com> wrote:

> > >I have a time-critical thing where the signal passes through an XC7A15 >FPGA and does a fair lot of stuff inside. I measured delay vs some >voltages: > >1.8 aux no measurable DC effect > >3.3 vccio no measurable DC effect > >2.5 vccio ditto (key io's are LVDS in this bank) > >+1 core -10 ps per millivolt! > >If I vary the trigger frequency, I can see the delay heterodyning >against the 1.8V switcher frequency, a few ps p-p maybe. Gotta track >that down. > >A spritz of freeze spray on the chip had practically no effect on >delay through the chip, on a scope at 100 ps/div. > >I expected sensitivity to core voltage, so we'll make sure we have a >serious, analog-quality voltage regulator next rev. > >The temperature thing surprised me. I was used to CMOS having a >serious positive delay TC. Maybe modern FPGAs have some sort of >temperature compensation designed in? > >We also have a ZYNQ on this board that crashes the ARM core >erratically, especially when the chip is hot. It might crash in maybe >a half hour MTBF if the chip reports 55C internally; the FPGA part >keeps going. At powerup boot from an SD card, it will always configure >the PL FPGA side, but will then fail to run our application if the >chip is hot. We're playing with DRAM and CPU clock rates to see if >that has much effect. > >
Fixed both problems. Jitter: replaced the 1.8V Vccaux switcher with a linear regulator. Temperature-dependant crashing: I found an oscillation on the Zynq 1v core power supply, about 100 mV p-p and 80 KHz. Putting a lot more capacitance at the switcher output kills that and makes the crash go away. The regulator design followed a chart in the LTM8078 data sheet. A Spice sim with the original values looks stable, no oscillation and a clean load-step recovery. There are other indications that ADI's Spice model of the LTM8078 is less than perfect. I think ADI is struggling to add a lot of new parts to the LT Spice libraries. Mike E in an interview suggested that rushing them out was compromising quality. Then he quit. Glad I fixed this this way. Guys were snooping the AXIbus and Linux at great expense and no progress.