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Achronix Semiconductor in Talks for Merger

Started by gnua...@gmail.com January 6, 2021
An IPO of sorts really.  They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors.  

Achronix has been profitable, so this should be a good deal.  I'm looking to buy in. 

-- 

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209 
On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com=
 wrote:
> An IPO of sorts really. They would merge with ACE Convergence Acquisition=
Corp NASDAQ: ACEV and this company would be seeking investors.=20
>=20 > Achronix has been profitable, so this should be a good deal. I'm looking =
to buy in.=20
>=20 > --=20 >=20 > Rick C.=20 >=20 > - Get 1,000 miles of free Supercharging=20 > - Tesla referral code - https://ts.la/richard11209
These IPOs done through SPACs are trying to take advantage of market exuber= ance which will surely pass at some point. It might be easy to get burned = when everything turns. I'm suspicious of new fads in the dark financial ar= ts. I don't know much about Achronix, except that I believe they no longer use = any of the asynchronous architecture on which they were originally based. = Maybe they should change their name to Chronix? But that sounds like Dr. D= re album or a persistent disease. I'm not sure how they survive in a marke= t ruled by the duopoly, but they must be doing something OK, since they're = still around.
On Thursday, January 7, 2021 at 5:24:34 PM UTC-5, Kevin Neilson wrote:
> On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.c=
om wrote:=20
> > An IPO of sorts really. They would merge with ACE Convergence Acquisiti=
on Corp NASDAQ: ACEV and this company would be seeking investors.=20
> >=20 > > Achronix has been profitable, so this should be a good deal. I'm lookin=
g to buy in.=20
> >=20 > > --=20 > >=20 > > Rick C.=20 > >=20 > > - Get 1,000 miles of free Supercharging=20 > > - Tesla referral code - https://ts.la/richard11209 > These IPOs done through SPACs are trying to take advantage of market exub=
erance which will surely pass at some point. It might be easy to get burned= when everything turns. I'm suspicious of new fads in the dark financial ar= ts.=20 Sounds like the POs from Tesla.=20
> I don't know much about Achronix, except that I believe they no longer us=
e any of the asynchronous architecture on which they were originally based.= Maybe they should change their name to Chronix? But that sounds like Dr. D= re album or a persistent disease. I'm not sure how they survive in a market= ruled by the duopoly, but they must be doing something OK, since they're s= till around. They seem to be doing a lot more than just OK. =20 --=20 Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
On 07/01/2021 22:24, Kevin Neilson wrote:
> On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote: >> An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. >> >> Achronix has been profitable, so this should be a good deal. I'm looking to buy in. >> >> -- >> >> Rick C. >> >> - Get 1,000 miles of free Supercharging >> - Tesla referral code - https://ts.la/richard11209 > > These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I'm suspicious of new fads in the dark financial arts. > > I don't know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I'm not sure how they survive in a market ruled by the duopoly,
They moved to a different market, their main product is an embedded FPGA IP core (and associated expensive to develop backend tools). Given the cost of making an ASIC/SoC and time to market pressures it makes sense to add some reconfigurable bits so you can fix some "oopses" and add features after tape-out. Hans www.ht-lab.com but they must be doing something OK, since they're still around.
>
On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:
> On 07/01/2021 22:24, Kevin Neilson wrote:=20 > > On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail=
.com wrote:=20
> >> An IPO of sorts really. They would merge with ACE Convergence Acquisit=
ion Corp NASDAQ: ACEV and this company would be seeking investors.=20
> >>=20 > >> Achronix has been profitable, so this should be a good deal. I'm looki=
ng to buy in.=20
> >>=20 > >> --=20 > >>=20 > >> Rick C.=20 > >>=20 > >> - Get 1,000 miles of free Supercharging=20 > >> - Tesla referral code - https://ts.la/richard11209=20 > >=20 > > These IPOs done through SPACs are trying to take advantage of market ex=
uberance which will surely pass at some point. It might be easy to get burn= ed when everything turns. I'm suspicious of new fads in the dark financial = arts.=20
> >=20 > > I don't know much about Achronix, except that I believe they no longer =
use any of the asynchronous architecture on which they were originally base= d. Maybe they should change their name to Chronix? But that sounds like Dr.= Dre album or a persistent disease. I'm not sure how they survive in a mark= et ruled by the duopoly,
> They moved to a different market, their main product is an embedded FPGA=
=20
> IP core (and associated expensive to develop backend tools). Given the=20 > cost of making an ASIC/SoC and time to market pressures it makes sense=20 > to add some reconfigurable bits so you can fix some "oopses" and add=20 > features after tape-out.=20
I don't think it is the "oopsies" problem they are addressing. If you have= an "oopsie" it is unlikely to be fixable with a separate piece of logic. = Allowing an ASIC user to add a bit of logic to the device or even a custom = coprocessor can be very useful. I seem to recall someone offering such a c= hip once, but I don't recall any details. It never made it to a general ma= rket that I know of. I suspect it was mostly sold to OEMs with high volume= s. Often FPGAs are used as prototyping devices and that may have been how = this was used.=20 --=20 Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:
> On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote: >> On 07/01/2021 22:24, Kevin Neilson wrote: >>> On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gmail.com wrote: >>>> An IPO of sorts really. They would merge with ACE Convergence Acquisition Corp NASDAQ: ACEV and this company would be seeking investors. >>>> >>>> Achronix has been profitable, so this should be a good deal. I'm looking to buy in. >>>> >>>> -- >>>> >>>> Rick C. >>>> >>>> - Get 1,000 miles of free Supercharging >>>> - Tesla referral code - https://ts.la/richard11209 >>> >>> These IPOs done through SPACs are trying to take advantage of market exuberance which will surely pass at some point. It might be easy to get burned when everything turns. I'm suspicious of new fads in the dark financial arts. >>> >>> I don't know much about Achronix, except that I believe they no longer use any of the asynchronous architecture on which they were originally based. Maybe they should change their name to Chronix? But that sounds like Dr. Dre album or a persistent disease. I'm not sure how they survive in a market ruled by the duopoly, >> They moved to a different market, their main product is an embedded FPGA >> IP core (and associated expensive to develop backend tools). Given the >> cost of making an ASIC/SoC and time to market pressures it makes sense >> to add some reconfigurable bits so you can fix some "oopses" and add >> features after tape-out. > > I don't think it is the "oopsies" problem they are addressing. If you have an "oopsie" it is unlikely to be fixable with a separate piece of logic.
No that is exactly what it is used for. By adding bypass logic to an "eFPGA" there is a good change you can fix bugs after tape-out. And yes designers do know which blocks are most likely to have issues. This is obviously not new, microprocessor manufacturers have been doing this for decades. I am always amazed at the issues AMD and Intel can fix after tape-out, I am sure the patched microcode is not just some simple ROM code that changes the instruction sequencer. Hans www.ht-lab.com Allowing an ASIC user to add a bit of logic to the device or even a custom coprocessor can be very useful. I seem to recall someone offering such a chip once, but I don't recall any details. It never made it to a general market that I know of. I suspect it was mostly sold to OEMs with high volumes. Often FPGAs are used as prototyping devices and that may have been how this was used.
>
On Saturday, January 9, 2021 at 4:31:18 AM UTC-5, HT-Lab wrote:
> On 08/01/2021 18:46, gnuarm.del...@gmail.com wrote:=20 > > On Friday, January 8, 2021 at 7:37:33 AM UTC-5, HT-Lab wrote:=20 > >> On 07/01/2021 22:24, Kevin Neilson wrote:=20 > >>> On Wednesday, January 6, 2021 at 11:35:39 AM UTC-7, gnuarm.del...@gma=
il.com wrote:=20
> >>>> An IPO of sorts really. They would merge with ACE Convergence Acquis=
ition Corp NASDAQ: ACEV and this company would be seeking investors.=20
> >>>>=20 > >>>> Achronix has been profitable, so this should be a good deal. I'm loo=
king to buy in.=20
> >>>>=20 > >>>> --=20 > >>>>=20 > >>>> Rick C.=20 > >>>>=20 > >>>> - Get 1,000 miles of free Supercharging=20 > >>>> - Tesla referral code - https://ts.la/richard11209=20 > >>>=20 > >>> These IPOs done through SPACs are trying to take advantage of market =
exuberance which will surely pass at some point. It might be easy to get bu= rned when everything turns. I'm suspicious of new fads in the dark financia= l arts.=20
> >>>=20 > >>> I don't know much about Achronix, except that I believe they no longe=
r use any of the asynchronous architecture on which they were originally ba= sed. Maybe they should change their name to Chronix? But that sounds like D= r. Dre album or a persistent disease. I'm not sure how they survive in a ma= rket ruled by the duopoly,=20
> >> They moved to a different market, their main product is an embedded FP=
GA=20
> >> IP core (and associated expensive to develop backend tools). Given the=
=20
> >> cost of making an ASIC/SoC and time to market pressures it makes sense=
=20
> >> to add some reconfigurable bits so you can fix some "oopses" and add=
=20
> >> features after tape-out.=20 > >=20 > > I don't think it is the "oopsies" problem they are addressing. If you h=
ave an "oopsie" it is unlikely to be fixable with a separate piece of logic= .
> No that is exactly what it is used for. By adding bypass logic to an=20 > "eFPGA" there is a good change you can fix bugs after tape-out. And yes=
=20
> designers do know which blocks are most likely to have issues.=20 >=20 > This is obviously not new, microprocessor manufacturers have been doing=
=20
> this for decades. I am always amazed at the issues AMD and Intel can fix=
=20
> after tape-out, I am sure the patched microcode is not just some simple=
=20
> ROM code that changes the instruction sequencer.=20 >=20 > Hans=20 > www.ht-lab.com > Allowing an ASIC user to add a bit of logic to the device or even a=20 > custom coprocessor can be very useful. I seem to recall someone=20 > offering such a chip once, but I don't recall any details. It never=20 > made it to a general market that I know of. I suspect it was mostly=20 > sold to OEMs with high volumes. Often FPGAs are used as prototyping=20 > devices and that may have been how this was used.=20
Do you have any info from Achronix regarding this? While the technique is = not uncommon in various devices, I don't think they are very large pieces o= f logic. If they aren't large, is it really important to have the fastest = technology in them (which is the Achronix advantage)? =20 There was a device made by a European chip company that had embedded FPGA. = I never saw anything about it being to "fix" the chip. =20 If the chip is being used for prototyping, that is entirely different and n= ot an ASIC at all. Why design a chip to debug the chip you are going to de= sign? What they do talk about at the Achronix web site is lots and lots of= "networking" and some very high speed interfaces. Rather than fixings opp= sies, I expect they are supporting leaving portions of the your ASIC to be = implemented in gate software rather than hard wiring. That would seem to m= ake a lot more sense.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
HT-Lab <hans64@htminuslab.com> wrote:
> They moved to a different market, their main product is an embedded FPGA > IP core (and associated expensive to develop backend tools). Given the > cost of making an ASIC/SoC and time to market pressures it makes sense > to add some reconfigurable bits so you can fix some "oopses" and add > features after tape-out.
Is an FPGA a good fit for that? It's not unusual to add 'chicken bits' that allow particular parts to be disabled or bypassed. But ISTM there's a bit of a disconnect between that and a full-scale FPGA. Unless you implement your entire block in FPGA logic, it's always going to be faster to implement your risky logic in several hard-logic ways and use routing controlled by chicken bits to select. You pay an area cost for that, but retain ASIC performance - I'd imagine even the best FPGA logic is going to be much slower. I could see some FPGA use cases where you want to do, say, hardware video decode (for power reasons perhaps) but need to periodically update to the latest codec. Similarly when doing packet processing and you need something to handle the customer's special flavour of packets at line rate. But going embedded FPGA means you pay a performance cost over hard ASIC cells, and you'll pay that performance cost even if everything works first time. I can't quite see going FPGA making sense for speculative bug fixes alone. Theo
Theo <theom+news@chiark.greenend.org.uk> writes:

> HT-Lab <hans64@htminuslab.com> wrote: >> They moved to a different market, their main product is an embedded FPGA >> IP core (and associated expensive to develop backend tools). Given the >> cost of making an ASIC/SoC and time to market pressures it makes sense >> to add some reconfigurable bits so you can fix some "oopses" and add >> features after tape-out. > > Is an FPGA a good fit for that?
I'd like to know too. Or actually I'd like to know the size of the eFPGA market, the customers and who has what market share and what it's actually used for but all that seems secret. But there are new(ish) companies exclusively in that market, at least Flex Logix (although they've come out with some kind of ML FPGA chip now) and some old ones have joined up too. Even FPGA old timer QuickLogic came out of what I think of near death to play in that business.
On Sunday, January 10, 2021 at 1:47:08 PM UTC-5, Anssi Saari wrote:
> Theo <theom...@chiark.greenend.org.uk> writes:=20 >=20 > > HT-Lab <han...@htminuslab.com> wrote:=20 > >> They moved to a different market, their main product is an embedded FP=
GA=20
> >> IP core (and associated expensive to develop backend tools). Given the=
=20
> >> cost of making an ASIC/SoC and time to market pressures it makes sense=
=20
> >> to add some reconfigurable bits so you can fix some "oopses" and add=
=20
> >> features after tape-out.=20 > >=20 > > Is an FPGA a good fit for that? > I'd like to know too. Or actually I'd like to know the size of the eFPGA=
=20
> market, the customers and who has what market share and what it's=20 > actually used for but all that seems secret. But there are new(ish)=20 > companies exclusively in that market, at least Flex Logix (although=20 > they've come out with some kind of ML FPGA chip now) and some old ones=20 > have joined up too. Even FPGA old timer QuickLogic came out of what I=20 > think of near death to play in that business.
What I've found interesting is there are very limited options for MCU/FPGA = combinations. The available choices are rather large and expensive. Like = there are <$5 FPGAs and very cheap MCUs, you'd think there would be <$5 MCU= /FPGA combos. Actually, Gowin has a line of small FPGAs with an ARM CM3. = I need to look into these a bit harder. I don't know if you can trust the = pricing on the Edge web site, but they show a 9 kLUT part with the ARM for = under $4. That's pretty interesting. The version without extra RAM is ava= ilable in an 88 pin package. The version with the RAM is not available in = anything larger than 48 pins at the moment without going to a BGA type pack= age.=20 --=20 Rick C. +- Get 1,000 miles of free Supercharging +- Tesla referral code - https://ts.la/richard11209