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Is there a way in Verilog to refer to a slice of an array?

Started by Kevin Simonson November 5, 2020
I've got two Verilog modules that look like this:

module queue
  ( output [ 64:0] dataOut
  , input          reset
  , input          shift
  , input  [ 64:0] dataIn);
...
endmodule

and

module lessThan
  ( output        lssThn
  , input [ 48:0] leftOp
  , input [ 48:0] rightOp);
...
endmodule

I've got six instances of module (queue) and need to pipe the forty-nine mo=
st significant bits of the output of each of two (queue)s to the two inputs=
 of (lessThan). Is there a way to refer to that forty-nine-bit slice? Or do=
 I have to do something like this:

module hmm ();

wire rs, shLf, shRg;
wire lfOut [ 64:0], lfIn [ 64:0];
wire rgOut [ 64:0], rgIn [ 64:0];
wire rgMsbs [ 48:0], lfMsbs [ 48:0];

queue lfq( lfOut, rs, shLf, lfIn);
queue rgq( rgOut, rs, shRg, rgIn);

lessThan lfLtRg( result, lfMsbs, rgMsbs);

generate
  for (bit =3D 0; bit <=3D 48; bit =3D bit + 1)
  begin
    assign lfMsbs[ bit] =3D lfOut[ bit + 16];
    assign rgMsbs[ bit] =3D rgOut[ bit + 16];
  end
endgenerate

endmodule