Forums

adding FPGA grounds

Started by Unknown October 11, 2020
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.



-- 

John Larkin         Highland Technology, Inc

Science teaches us to doubt.

  Claude Bernard
  
On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote:
> One of my guys is suggesting that we ground unused balls on an FPGA > and compile them to be low outputs, the idea being to reduce ground > impedance and add some damping. > > Has anyone done this? Does it help? > > I guess I could have an input that controls the tri-states of all such > pins, and also bring out one logic-low to scope, and turn the grounds > on and off and see if it makes any difference. > > It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least > another 30 fake grounds. >
I have seen some manufactures suggest this. I haven't measured it, but I would guess it could help, at least as long as the FPGA doesn't every try to drive the output high for a moment.
On Sunday, October 11, 2020 at 7:17:09 PM UTC-4, jla...@highlandsniptechnol=
ogy.com wrote:
> One of my guys is suggesting that we ground unused balls on an FPGA > and compile them to be low outputs, the idea being to reduce ground > impedance and add some damping. >=20 > Has anyone done this? Does it help? >=20 > I guess I could have an input that controls the tri-states of all such > pins, and also bring out one logic-low to scope, and turn the grounds > on and off and see if it makes any difference. >=20 > It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least > another 30 fake grounds.
What problem are you trying to solve? My experience is when it comes to po= wer distribution systems (PDS) people often try to optimize without knowing= if they have a problem. PDS design is one of those things where you can e= ither try actually analyzing the design to know how to design the PDS, or y= ou can throw in a lot of overkill to try to make sure you hit the rabbit. = =20 What will you measure to see the effectiveness of the grounds? The usual c= oncern is ground bounce. For that you would measure an output pulled low w= ith no trace to see (as well as possible) the internal ground voltage. I'm= not sure how well the internal spike will be conducted through the pin dri= vers. Otherwise you would need to load a design into the chip that would p= roduce similar switching spikes as your real design and see if you get any = false triggers on clocks or input corruptions. I suppose a simple input di= rectly driving an output can show a corrupted input level differently than = an output at a fixed low level showing the ground bounce directly.=20 --=20 Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
On Sunday, October 11, 2020 at 8:36:53 PM UTC-4, Richard Damon wrote:
> On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote: > > One of my guys is suggesting that we ground unused balls on an FPGA > > and compile them to be low outputs, the idea being to reduce ground > > impedance and add some damping. > > > > Has anyone done this? Does it help? > > > > I guess I could have an input that controls the tri-states of all such > > pins, and also bring out one logic-low to scope, and turn the grounds > > on and off and see if it makes any difference. > > > > It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least > > another 30 fake grounds. > > > > I have seen some manufactures suggest this. I haven't measured it, but I > would guess it could help, at least as long as the FPGA doesn't every > try to drive the output high for a moment.
For the final design the outputs would be hardwired to ground eliminating the possibility of driving to any other state. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
On 10/12/20 12:40 AM, Rick C wrote:
> On Sunday, October 11, 2020 at 8:36:53 PM UTC-4, Richard Damon wrote: >> On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote: >>> One of my guys is suggesting that we ground unused balls on an FPGA >>> and compile them to be low outputs, the idea being to reduce ground >>> impedance and add some damping. >>> >>> Has anyone done this? Does it help? >>> >>> I guess I could have an input that controls the tri-states of all such >>> pins, and also bring out one logic-low to scope, and turn the grounds >>> on and off and see if it makes any difference. >>> >>> It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least >>> another 30 fake grounds. >>> >> >> I have seen some manufactures suggest this. I haven't measured it, but I >> would guess it could help, at least as long as the FPGA doesn't every >> try to drive the output high for a moment. > > For the final design the outputs would be hardwired to ground eliminating the possibility of driving to any other state. >
If they were 'hard wired' they wouldn't be programmable! The issue is that if in the configuration process, it was possible for a momentary glitch to turn on the high driver, you would get a current spike. They do try to avoid this, but sometimes, particularly during the power on transient, strange things can happen. Some parts definitely will turn on weak pull ups which will draw power till they get the pull ups configured off.
In comp.arch.fpga jlarkin@highlandsniptechnology.com wrote:
> One of my guys is suggesting that we ground unused balls on an FPGA > and compile them to be low outputs, the idea being to reduce ground > impedance and add some damping. > > Has anyone done this? Does it help? > > I guess I could have an input that controls the tri-states of all such > pins, and also bring out one logic-low to scope, and turn the grounds > on and off and see if it makes any difference. > > It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least > another 30 fake grounds. >
If some Nvidia ^H^H^H^H^H Xilinx documents proposes, consider it. Otherwise not! -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 1623569 ------- Fax. 06151 1623305 ---------
On Monday, October 12, 2020 at 8:40:57 AM UTC-4, Richard Damon wrote:
> On 10/12/20 12:40 AM, Rick C wrote: > > On Sunday, October 11, 2020 at 8:36:53 PM UTC-4, Richard Damon wrote: > >> On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote: > >>> One of my guys is suggesting that we ground unused balls on an FPGA > >>> and compile them to be low outputs, the idea being to reduce ground > >>> impedance and add some damping. > >>> > >>> Has anyone done this? Does it help? > >>> > >>> I guess I could have an input that controls the tri-states of all such > >>> pins, and also bring out one logic-low to scope, and turn the grounds > >>> on and off and see if it makes any difference. > >>> > >>> It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least > >>> another 30 fake grounds. > >>> > >> > >> I have seen some manufactures suggest this. I haven't measured it, but I > >> would guess it could help, at least as long as the FPGA doesn't every > >> try to drive the output high for a moment. > > > > For the final design the outputs would be hardwired to ground eliminating the possibility of driving to any other state. > > > If they were 'hard wired' they wouldn't be programmable! The issue is > that if in the configuration process, it was possible for a momentary > glitch to turn on the high driver, you would get a current spike. They > do try to avoid this, but sometimes, particularly during the power on > transient, strange things can happen. Some parts definitely will turn on > weak pull ups which will draw power till they get the pull ups > configured off.
There are protections in the chip to prevent loading a corrupt bitstream. This isn't just a simple SPI register load. No pull up to the power rail burning up an I/O. -- Rick C. -- Get 1,000 miles of free Supercharging -- Tesla referral code - https://ts.la/richard11209
How do you know these pins are not some sort of manufacturing test output pins?

On a networking chip I used (years ago), a couple of the pins that were 
documented  as power and ground pins were actually mode configuration pins.   

> One of my guys is suggesting that we ground unused balls on an FPGA > and compile them to be low outputs, the idea being to reduce ground > impedance and add some damping.
On Monday, October 12, 2020 at 12:52:19 PM UTC-4, Jim Lewis wrote:
> How do you know these pins are not some sort of manufacturing test output=
pins?
>=20 > On a networking chip I used (years ago), a couple of the pins that were=
=20
> documented as power and ground pins were actually mode configuration pin=
s. =20 He is talking about wiring unused I/O pins that he can specify as grounds o= r power by assigning a '0' or '1' respectively. They are not the same as a= solid connection to the chip ground or power, but every bit helps. At hig= h frequency the pin inductance is probably higher impedance than the resist= ance of the internal MOSFET, so the I/O grounds are probably a lot better t= han nothing. But this is also needed on the I/O power supply as well as gr= ound.=20 --=20 Rick C. -+ Get 1,000 miles of free Supercharging -+ Tesla referral code - https://ts.la/richard11209
On 10/12/20 10:05 AM, Rick C wrote:
> On Monday, October 12, 2020 at 8:40:57 AM UTC-4, Richard Damon wrote: >> On 10/12/20 12:40 AM, Rick C wrote: >>> On Sunday, October 11, 2020 at 8:36:53 PM UTC-4, Richard Damon wrote: >>>> On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote: >>>>> One of my guys is suggesting that we ground unused balls on an FPGA >>>>> and compile them to be low outputs, the idea being to reduce ground >>>>> impedance and add some damping. >>>>> >>>>> Has anyone done this? Does it help? >>>>> >>>>> I guess I could have an input that controls the tri-states of all such >>>>> pins, and also bring out one logic-low to scope, and turn the grounds >>>>> on and off and see if it makes any difference. >>>>> >>>>> It's an XC7A15T-1FTG256C with 30 ground pins. We could add at least >>>>> another 30 fake grounds. >>>>> >>>> >>>> I have seen some manufactures suggest this. I haven't measured it, but I >>>> would guess it could help, at least as long as the FPGA doesn't every >>>> try to drive the output high for a moment. >>> >>> For the final design the outputs would be hardwired to ground eliminating the possibility of driving to any other state. >>> >> If they were 'hard wired' they wouldn't be programmable! The issue is >> that if in the configuration process, it was possible for a momentary >> glitch to turn on the high driver, you would get a current spike. They >> do try to avoid this, but sometimes, particularly during the power on >> transient, strange things can happen. Some parts definitely will turn on >> weak pull ups which will draw power till they get the pull ups >> configured off. > > There are protections in the chip to prevent loading a corrupt bitstream. This isn't just a simple SPI register load. > > No pull up to the power rail burning up an I/O. >
Maybe newer FPGAs have less problems with it, but I seem to remember that some FPGAs comming out of configuration (and defaulting to be an input) into an output, always enabled, driving low, might not complete keep the high side driver off. These FPGAs specifically defined that unused pins should be left floating/not connected. IF the chip designer is presuming that small glitches on enabled output are unimportant (since they will only be driving inputs), this isn't unreasonable. Later, with higher density packages, the idea that grounding low driving outputs could improve (slightly) the ground impedance, made it more important to avoid these issues.