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VHDL2019 Webinars

Started by HT-Lab April 30, 2021
In case you missed it Aldec (Jim Lewis) is doing a webinars series on 
VHDL2019.

https://www.aldec.com/en/company/events

It looks like I missed the first one as it start with Part2,

Regards,
Hans.
www.ht-lab.com

HT-Lab wrote:

> In case you missed it Aldec (Jim Lewis) is doing a webinars series on > VHDL2019.
Thanks, but honestly, who would benefit from learning VHDL2019 if VHDL2008 is still supported at the so-so level at best? My grandchildren? Same with System Verilog. Best regards, Piotr
On 01/05/2021 07:51, Piotr Wyderski wrote:
> HT-Lab wrote: > >> In case you missed it Aldec (Jim Lewis) is doing a webinars series on >> VHDL2019. > > Thanks, but honestly, who would benefit from learning VHDL2019 if > VHDL2008 is still supported at the so-so level at best? My > grandchildren? Same with System Verilog.
Hi Piotr, I assume you are using Vivado's simulator? in that case yes support is not that great but it is the price you pay for free. Both Siemens and Aldec have close to full support for VHDL2008 and SV2017 and Incisive and VCS have (so I have been told) "acceptable" VHDL2008 support and obviously perfect SV support. Unfortunately everybody is so busy producing code that they forget that new language constructs can really help their coding effort and reduce bugs. Try telling a VHDL user that he can no longer use process(all)/case?/reading output ports/etc and see how he/she responds. The same will apply to VHDL2019, there will be language features that everybody will use. Watch the webinar, see which features you like then log an enhancement request with your simulator supplier, it is worth the effort! Regards, Hans. www.ht-lab.com
> >     Best regards, Piotr
Hi Hans,

> I assume you are using Vivado's simulator?
Actually, at the moment it is Lattice Diamond and Lattice Radiant, as the FPGA is used mostly for its high-speed LVDS capabilities.
> in that case yes support is not that great but it is the price you pay for free.
I must admit that I do not quite follow this argument. In the software world I can get both GCC and Clang entirely for free with an almost full set of C++ features, often years before the new standard is accepted. I have no idea why it should not be the same way with EDA tools. And the tools are not free, I have already paid for them buying the chips. This is not something I would like to spend too much time on, though; voting with my feet is usually the best solution.
> Unfortunately everybody is so busy producing code that they forget that > new language constructs can really help their coding effort and reduce > bugs.
I wanted to use the new language constructs, but then the tools refused to interpret them. Writing something that is recognisable by ModelSim, Synplify and the Lattice in-house compiler at the same time is a kind of an art. I had a similar experience with Quartus before.
> The same will apply to VHDL2019, there will be language features that > everybody will use.
Not necessarily everybody. I got really tired with the hopelessly obsolete HDL support and stared generating more and more HDL files from Python scripts, especially when heavy generic support is required. I believe I will further pursue this path rather than retract from it. It simply works and I no longer need to guess what subset of the newer standard was elected for implementation by throwing darts in the marketing department of a particular vendor. The output is VHDL93 and if something doesn't work, it doesn't work on my end -- I can add arbitrary amount of Python preprocessing to fix that.
> Watch the webinar, see which features you like then log an enhancement > request with your simulator supplier, it is worth the effort!
Last time I did that the supplier asked me how many devices I was planning to purchase and what was the purpose of the product. I couldn't find any logical connection between the question I asked and the response I got, so I decided that any further contact would be pointless. Best regards, Piotr
On Sunday, May 2, 2021 at 8:36:36 AM UTC-7, Piotr Wyderski wrote:
> Hi Hans, > > I assume you are using Vivado's simulator? > Actually, at the moment it is Lattice Diamond and Lattice Radiant, as > the FPGA is used mostly for its high-speed LVDS capabilities. > > in that case yes support is not that great but it is the price you pay for free. > I must admit that I do not quite follow this argument. In the software > world I can get both GCC and Clang entirely for free with an almost full > set of C++ features, often years before the new standard is accepted. I > have no idea why it should not be the same way with EDA tools. And the > tools are not free, I have already paid for them buying the chips. This > is not something I would like to spend too much time on, though; voting > with my feet is usually the best solution. > > Unfortunately everybody is so busy producing code that they forget that > > new language constructs can really help their coding effort and reduce > > bugs. > I wanted to use the new language constructs, but then the tools refused > to interpret them. Writing something that is recognisable by ModelSim, > Synplify and the Lattice in-house compiler at the same time is a kind of > an art. I had a similar experience with Quartus before. > > The same will apply to VHDL2019, there will be language features that > > everybody will use. > Not necessarily everybody. I got really tired with the hopelessly > obsolete HDL support and stared generating more and more HDL files from > Python scripts, especially when heavy generic support is required. I > believe I will further pursue this path rather than retract from it. > It simply works and I no longer need to guess what subset of the newer > standard was elected for implementation by throwing darts in the > marketing department of a particular vendor. The output is VHDL93 and if > something doesn't work, it doesn't work on my end -- I can add arbitrary > amount of Python preprocessing to fix that. > > Watch the webinar, see which features you like then log an enhancement > > request with your simulator supplier, it is worth the effort! > Last time I did that the supplier asked me how many devices I was > planning to purchase and what was the purpose of the product. I couldn't > find any logical connection between the question I asked and the > response I got, so I decided that any further contact would be pointless. > > Best regards, Piotr
I like to let Jim transfer all Webinars to Youtube so that everyone at any time at any place can view his presentation. I like many Webinars presentations, but mostly I miss all interesting subjects, because it provides the presentation at a fixed time, and one cannot review it again later. Weng
On Friday, April 30, 2021 at 4:49:37 AM UTC-4, HT-Lab wrote:
> In case you missed it Aldec (Jim Lewis) is doing a webinars series on > VHDL2019. > > https://www.aldec.com/en/company/events > > It looks like I missed the first one as it start with Part2,
Yeah, so was there a part 1? Anyone know? I got confused signing up. I didn't see the US/EU at the end of the titles and thought 3:00 CEST was US central time... lol. So I'm signed up for both times on all three remaining lectures. -- Rick C. - Get 1,000 miles of free Supercharging - Tesla referral code - https://ts.la/richard11209
"gnuarm.del...@gmail.com" <gnuarm.deletethisbit@gmail.com> writes:

> On Friday, April 30, 2021 at 4:49:37 AM UTC-4, HT-Lab wrote: >> In case you missed it Aldec (Jim Lewis) is doing a webinars series on >> VHDL2019. >> >> https://www.aldec.com/en/company/events >> >> It looks like I missed the first one as it start with Part2, > > Yeah, so was there a part 1? Anyone know?
Sure and there's a recording of it at https://www.aldec.com/en/support/resources/multimedia/webinars?type=1&products=&category=5&sub_category=&page=6 I haven't watched more than a few minutes yet.
On Thursday, May 6, 2021 at 9:11:38 AM UTC-4, Anssi Saari wrote:
> "gnuarm.del...@gmail.com" <gnuarm.del...@gmail.com> writes: > > > On Friday, April 30, 2021 at 4:49:37 AM UTC-4, HT-Lab wrote: > >> In case you missed it Aldec (Jim Lewis) is doing a webinars series on > >> VHDL2019. > >> > >> https://www.aldec.com/en/company/events > >> > >> It looks like I missed the first one as it start with Part2, > > > > Yeah, so was there a part 1? Anyone know? > Sure and there's a recording of it at > https://www.aldec.com/en/support/resources/multimedia/webinars?type=1&products=&category=5&sub_category=&page=6 > > I haven't watched more than a few minutes yet.
I guess I'll have to watch today's seminar on video too since they have not sent any info on how to watch it live and it's coming up in 10 minutes. -- Rick C. + Get 1,000 miles of free Supercharging + Tesla referral code - https://ts.la/richard11209
On 04/05/2021 16:07, W TX wrote:
> On Sunday, May 2, 2021 at 8:36:36 AM UTC-7, Piotr Wyderski wrote:
..
>> >> Best regards, Piotr > I like to let Jim transfer all Webinars to Youtube so that everyone at any time at any place can view his presentation. > > I like many Webinars presentations, but mostly I miss all interesting subjects, because it provides the presentation at a fixed time, and one cannot review it again later. > > Weng
Hi Weng, Not sure which webinars you signed up for but I nearly always get a link to watch the webinar again. The last 3 where Doulos, Microchip and DVclub and they all send me a link to watch it again. I am not sure youtube is any better platform given the excessive adverts I am getting lately (might be because I also click skip ads as quick as possible.....) Hans www.ht-lab.com
> > >