Intel ModelSim Starter Edition is available free now!

On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
> On 25/05/2021 10:47, Tianxiang Weng wrote: 
> > On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote: 
> >> On 25/05/2021 06:18, Tianxiang Weng wrote: 
> >> .. 
> >>>>
> .
> > 
> > Hans, 
> > I copy the file generated by the command vcom -help all. 
> > 
> > I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit. 
> > 
> > What should I do? 
> >
> start reading: 
> 
> <your_modelsim_installation_dir>/docs/pdfdocs/modelsim_tut.pdf 
> 
> Regards, 
> Hans 
> www.ht-lab.com

Hans,

Thank you for your guide. 

I have downloaded the files, the version is 2012, 10.c. 
Is it the latest version available from the web?

Weng

On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote: 
> > On 25/05/2021 10:47, Tianxiang Weng wrote: 
> > > On Tuesday, May 25, 2021 at 12:07:37 AM UTC-7, HT-Lab wrote: 
> > >> On 25/05/2021 06:18, Tianxiang Weng wrote: 
> > >> .. 
> > >>>> 
> > . 
> > > 
> > > Hans, 
> > > I copy the file generated by the command vcom -help all. 
> > > 
> > > I search "do", 18 hits, there is no do file format; I searched "tcl", there is no-hit. 
> > > 
> > > What should I do? 
> > > 
> > start reading: 
> > 
> > <your_modelsim_installation_dir>/docs/pdfdocs/modelsim_tut.pdf 
> > 
> > Regards, 
> > Hans 
> > www.ht-lab.com
> Hans, 
> 
> Thank you for your guide. 
> 
> I have downloaded the files, the version is 2012, 10.c. 
> Is it the latest version available from the web? 
> 
> Weng

Hi Hans,
After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files/ModelSim_tutorial.pdf, I decided to abandon any attempt to use the command-line method. 

The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method. There is no good luck with it.

Thank you.

Weng

On 25/05/2021 20:32, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
..
> 
> Thank you for your guide.
> 
> I have downloaded the files, the version is 2012, 10.c.
> Is it the latest version available from the web?

No it should be 2020.3,

Regards,
Hans.

> 
> Weng
> 

On Tuesday, May 25, 2021 at 11:17:10 PM UTC-7, HT-Lab wrote:
> On 25/05/2021 20:32, Tianxiang Weng wrote: 
> > On Tuesday, May 25, 2021 at 9:33:13 AM UTC-7, HT-Lab wrote:
> ..
> > 
> > Thank you for your guide. 
> > 
> > I have downloaded the files, the version is 2012, 10.c. 
> > Is it the latest version available from the web?
> No it should be 2020.3, 
> 
> Regards, 
> Hans. 
> 
> > 
> > Weng 
> >

Hans,

Could you give a link to 2020.3?

Weng

On 26/05/2021 06:21, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
..
> 
> Hi Hans,
> After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files

Verilog?

/ModelSim_tutorial.pdf, I decided to abandon any attempt to use the 
command-line method.
> 
> The reason is very simple: if the Starter Edition ignores the -2008 parameter in using the icon method, it will ignore it in a command-line method. There is no good luck with it.

Not sure what you are doing but creating a Modelsim .do/.tcl file is 
dead simple, here is the procedure for a simple design:

1) Create a work library (this is done automatically as well)
vlib work work

2) Optionally but recommended create a local modelsim.ini file
vmap work work

3) compile your design
vcom -quiet -2008 myfiles.vhd
vlog -quiet myver.sv

4) elaborate the design
vsim -quiet work.mytestbench

5) open waveform (or open previous saved one with do wave.do)
view wave

6) drag and drop your signals in the waveform window and save

7) run your simulation
run -all

To re-iterate all OEM versions support VHDL2008,

Regards,
Hans
www.ht-lab.com


> 
> Thank you.
> 
> Weng
> 

On Tuesday, May 25, 2021 at 11:36:20 PM UTC-7, HT-Lab wrote:
> On 26/05/2021 06:21, Tianxiang Weng wrote:=20
> > On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:
> ..
> >=20
> > Hi Hans,=20
> > After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/We=
ng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files
> Verilog?
> /ModelSim_tutorial.pdf, I decided to abandon any attempt to use the=20
> command-line method.=20
> >=20
> > The reason is very simple: if the Starter Edition ignores the -2008 par=
ameter in using the icon method, it will ignore it in a command-line method=
. There is no good luck with it.
> Not sure what you are doing but creating a Modelsim .do/.tcl file is=20
> dead simple, here is the procedure for a simple design:=20
>=20
> 1) Create a work library (this is done automatically as well)=20
> vlib work work=20
>=20
> 2) Optionally but recommended create a local modelsim.ini file=20
> vmap work work=20
>=20
> 3) compile your design=20
> vcom -quiet -2008 myfiles.vhd=20
> vlog -quiet myver.sv=20
>=20
> 4) elaborate the design=20
> vsim -quiet work.mytestbench=20
>=20
> 5) open waveform (or open previous saved one with do wave.do)=20
> view wave=20
>=20
> 6) drag and drop your signals in the waveform window and save=20
>=20
> 7) run your simulation=20
> run -all=20
>=20
> To re-iterate all OEM versions support VHDL2008,=20
>=20
> Regards,=20
> Hans=20
> www.ht-lab.com=20
>=20
>=20
> >=20
> > Thank you.=20
> >=20
> > Weng=20
> >

Hi Hans,

Thank you very much, I appreciate your selfless efforts to help me.

I will try your method step by step and will report to you on this post for=
 further advice after step 3.

I have a FIFO entity., 108 source code lines, to test if the Starter Editio=
n allows using the VHDL-2008: eliminating a signal Full that drives the out=
put port Full_O. My experience is the Starter Edition gives a hint that an =
output port cannot be read internally and the function can be implemented i=
f it is compiled with the 2008 version set. Why I told you that the Starter=
 Edition does not support the 2008 version, is because of the generated hin=
t, i.t. after your step 3, I will immediately know if the Starter Edition s=
upports the 2008 version.

Actually, I may need a few more months to finish my project. I am about hal=
fway now to the finish line regarding the coding. With Starter Edition of M=
odelSim available now, I tried to compile my finished files to see if there=
 are any types of errors and do simulation for the finished algorithm.=20

My original plan is when all my coding is finished, I will purchase Intel M=
odelSim for the first year of $1999, then start compiling and simulating wi=
th the VHDL-2008 version and finish it within 1 year.

If you are more interested in what I am doing now, we may communicate perso=
nally through my email: w t x w t x @ g m a I . c o m.

Weng

On Wednesday, May 26, 2021 at 4:35:32 AM UTC-7, Tianxiang Weng wrote:
> On Tuesday, May 25, 2021 at 11:36:20 PM UTC-7, HT-Lab wrote:=20
> > On 26/05/2021 06:21, Tianxiang Weng wrote:=20
> > > On Tuesday, May 25, 2021 at 12:32:55 PM UTC-7, Tianxiang Weng wrote:=
=20
> > ..=20
> > >=20
> > > Hi Hans,=20
> > > After reading 6 pages of MIT ModelSim/Verilog Tutorial at file:///E:/=
Weng/00-Claim/00-Sorting/00-Simulation/ModelSim%20Files=20
> > Verilog?=20
> > /ModelSim_tutorial.pdf, I decided to abandon any attempt to use the=20
> > command-line method.=20
> > >=20
> > > The reason is very simple: if the Starter Edition ignores the -2008 p=
arameter in using the icon method, it will ignore it in a command-line meth=
od. There is no good luck with it.=20
> > Not sure what you are doing but creating a Modelsim .do/.tcl file is=20
> > dead simple, here is the procedure for a simple design:=20
> >=20
> > 1) Create a work library (this is done automatically as well)=20
> > vlib work work=20
> >=20
> > 2) Optionally but recommended create a local modelsim.ini file=20
> > vmap work work=20
> >=20
> > 3) compile your design=20
> > vcom -quiet -2008 myfiles.vhd=20
> > vlog -quiet myver.sv=20
> >=20
> > 4) elaborate the design=20
> > vsim -quiet work.mytestbench=20
> >=20
> > 5) open waveform (or open previous saved one with do wave.do)=20
> > view wave=20
> >=20
> > 6) drag and drop your signals in the waveform window and save=20
> >=20
> > 7) run your simulation=20
> > run -all=20
> >=20
> > To re-iterate all OEM versions support VHDL2008,=20
> >=20
> > Regards,=20
> > Hans=20
> > www.ht-lab.com=20
> >=20
> >=20
> > >=20
> > > Thank you.=20
> > >=20
> > > Weng=20
> > >
> Hi Hans,=20
>=20
> Thank you very much, I appreciate your selfless efforts to help me.=20
>=20
> I will try your method step by step and will report to you on this post f=
or further advice after step 3.=20
>=20
> I have a FIFO entity., 108 source code lines, to test if the Starter Edit=
ion allows using the VHDL-2008: eliminating a signal Full that drives the o=
utput port Full_O. My experience is the Starter Edition gives a hint that a=
n output port cannot be read internally and the function can be implemented=
 if it is compiled with the 2008 version set. Why I told you that the Start=
er Edition does not support the 2008 version, is because of the generated h=
int, i.t. after your step 3, I will immediately know if the Starter Edition=
 supports the 2008 version.=20
>=20
> Actually, I may need a few more months to finish my project. I am about h=
alfway now to the finish line regarding the coding. With Starter Edition of=
 ModelSim available now, I tried to compile my finished files to see if the=
re are any types of errors and do simulation for the finished algorithm.=20
>=20
> My original plan is when all my coding is finished, I will purchase Intel=
 ModelSim for the first year of $1999, then start compiling and simulating =
with the VHDL-2008 version and finish it within 1 year.=20
>=20
> If you are more interested in what I am doing now, we may communicate per=
sonally through my email: w t x w t x @ g m a I . c o m.=20
>=20
> Weng

Hans,
Here is the record of my compiling FIFO.vhd:

can't open "transcript": permission denied
# Reading pref.tcl
# Loading project FIFO
vcom -work work -2008 -explicit -stats=3Dnone FIFO.vhd
# Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.=
02 Feb  3 2021
# -- Loading package STANDARD
# -- Loading package TEXTIO
# -- Loading package std_logic_1164
# -- Loading package NUMERIC_STD
# -- Compiling entity FIFO
# -- Compiling architecture A of FIFO
# ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_=
STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED.
# ** Note: FIFO.vhd(120): VHDL Compiler exiting
# C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed.

The error is about a case statement:
case A & B is -- test this statement
... =20
end case;

In 2008,  A & B can be two different signals; In 2002,=20
case C is  -- C =3D A & B
...
end case;

In the Starter Edition, when ModelSim is being opened, one can only choose =
the "Jump Start" button to either create a project or open an existing proj=
ect. No other choice to select.

I selected the "Create a project" button. After the input is finished I ent=
er the following command line:
vcom -work work -2008 -explicit -stats=3Dnone FIFO.vhd

Is there anything I missed?

Weng

On 26/05/2021 17:41, Tianxiang Weng wrote:
..snip

Hi Weng,

> 
> Hans,
> Here is the record of my compiling FIFO.vhd:
> 
> can't open "transcript": permission denied

That is not good, do you have admin rights on your PC?

> # Reading pref.tcl
> # Loading project FIFO
> vcom -work work -2008 -explicit -stats=none FIFO.vhd
> # Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb  3 2021
> # -- Loading package STANDARD
> # -- Loading package TEXTIO
> # -- Loading package std_logic_1164
> # -- Loading package NUMERIC_STD
> # -- Compiling entity FIFO
> # -- Compiling architecture A of FIFO
> # ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED.
> # ** Note: FIFO.vhd(120): VHDL Compiler exiting
> # C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed.
> 
> The error is about a case statement:
> case A & B is -- test this statement
> ...
> end case;
> 
> In 2008,  A & B can be two different signals; In 2002,
> case C is  -- C = A & B
> ...
> end case;

Hard to tell what is going on, I would suggest you post your code on the 
comp.lang.vhdl


> In the Starter Edition, when ModelSim is being opened, one can only choose the "Jump Start" button to either create a project or open an existing project. No other choice to select.

I suspect it find an mpf file (your previous project perhaps) and hence 
defaults to using projects? Just delete/rename the mpf file and try 
again. If that fails then you can try to rename or delete the Modelsim 
registry entry:

HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim

When you rename/delete this entry Modelsim will recreate it when it
starts up and behaves as if it has just been installed.

> 
> I selected the "Create a project" button. After the input is finished I enter the following command line:
> vcom -work work -2008 -explicit -stats=none FIFO.vhd
> 
> Is there anything I missed?

Most likely but as I mentioned difficult to tell what is going on,

Good luck,
Hans.
www.ht-lab.com


> 
> Weng
> 

On Thursday, May 27, 2021 at 8:51:03 AM UTC-7, HT-Lab wrote:
> On 26/05/2021 17:41, Tianxiang Weng wrote: 
> ..snip 
> 
> Hi Weng,
> > 
> > Hans, 
> > Here is the record of my compiling FIFO.vhd: 
> > 
> > can't open "transcript": permission denied
> That is not good, do you have admin rights on your PC?
> > # Reading pref.tcl 
> > # Loading project FIFO 
> > vcom -work work -2008 -explicit -stats=none FIFO.vhd 
> > # Model Technology ModelSim - Intel FPGA Edition vcom 2021.1 Compiler 2021.02 Feb 3 2021 
> > # -- Loading package STANDARD 
> > # -- Loading package TEXTIO 
> > # -- Loading package std_logic_1164 
> > # -- Loading package NUMERIC_STD 
> > # -- Compiling entity FIFO 
> > # -- Compiling architecture A of FIFO 
> > # ** Error: FIFO.vhd(87): Ambiguous type in infix expression; ieee.NUMERIC_STD.UNRESOLVED_UNSIGNED or ieee.NUMERIC_STD.UNRESOLVED_SIGNED. 
> > # ** Note: FIFO.vhd(120): VHDL Compiler exiting 
> > # C:/intelFPGA_pro/21.1/modelsim_ase/win32aloem/vcom failed. 
> > 
> > The error is about a case statement: 
> > case A & B is -- test this statement 
> > ... 
> > end case; 
> > 
> > In 2008, A & B can be two different signals; In 2002, 
> > case C is -- C = A & B 
> > ... 
> > end case;
> Hard to tell what is going on, I would suggest you post your code on the 
> comp.lang.vhdl
> > In the Starter Edition, when ModelSim is being opened, one can only choose the "Jump Start" button to either create a project or open an existing project. No other choice to select.
> I suspect it find an mpf file (your previous project perhaps) and hence 
> defaults to using projects? Just delete/rename the mpf file and try 
> again. If that fails then you can try to rename or delete the Modelsim 
> registry entry: 
> 
> HKEY_CURRENT_USER\Software\Model Technology Incorporated\ModelSim 
> 
> When you rename/delete this entry Modelsim will recreate it when it 
> starts up and behaves as if it has just been installed.
> > 
> > I selected the "Create a project" button. After the input is finished I enter the following command line: 
> > vcom -work work -2008 -explicit -stats=none FIFO.vhd 
> > 
> > Is there anything I missed?
> Most likely but as I mentioned difficult to tell what is going on, 
> 
> Good luck, 
> Hans. 
> www.ht-lab.com 
> 
> 
> > 
> > Weng 
> >

Hans,

I created a new directory, an empty one, then copied a modified FIFO.vhd into the directory; after that, I started ModelSim and created a new project and got the result.

No, I don't want to continue any other things to try it again. 

Thank you.

Weng