A state machine design problem

Hi,

I have the following VHDL code for a state machine:

type Output_State_t is (

State_a,

State_b,

State_c);

signal Output_State, Output_State_NS : Output_State_t ;

At a clocked process, there is code with the Output_State:

p1: process(Clock, Reset)

begin

     if Reset then

         Output_State <= State_a;

     else

           Output_State <= Output_State_NS ;

     end if;

end process;

There is a non-clocked process at which Output_State_NS is generated. There is an output enable signal:

signal Output_Enable : std_logic; -- when it = '1', output is allowed, or not allowed if it = '0'.

p2: process(all)

begin

...

   A_O <= '0';  -- default values

   B_O <= '0';

   Output_State_NS <= Output_State;

        if Output_Enable = '1' then

	     case Output_State is

	             when State_a =>
                             A_O <= '1';

                            B_O <= '1';

                            if Condition_A then

                                    Output_State_NS <= State_b;

                           end if;

	          when State\_b =>
...

	    end case;

      end if;
end process;

on clock 1 both Output_Enable and Condition_A = '1', on clock 2, Output_Enable = '0'; In my ModelSim simulation the Output_State is at State_a, not at State_b on clock 2.

Why is it not at State_b?

Thank you.

Weng

On Thursday, July 8, 2021 at 7:56:39 AM UTC-7, Tianxiang Weng wrote:
> Hi, 
> 
> I have the following VHDL code for a state machine: 
> 
> type Output_State_t is ( 
> 
> State_a, 
> 
> State_b, 
> 
> State_c); 
> 
> signal Output_State, Output_State_NS : Output_State_t ; 
> 
> At a clocked process, there is code with the Output_State: 
> 
> p1: process(Clock, Reset) 
> 
> begin 
> 
> if Reset then 
> 
> Output_State <= State_a; 
> 
> else 
> 
> Output_State <= Output_State_NS ; 
> 
> end if; 
> 
> end process; 
> 
> There is a non-clocked process at which Output_State_NS is generated. There is an output enable signal: 
> 
> signal Output_Enable : std_logic; -- when it = '1', output is allowed, or not allowed if it = '0'. 
> 
> p2: process(all) 
> 
> begin 
> 
> ... 
> 
> A_O <= '0'; -- default values 
> 
> B_O <= '0'; 
> 
> Output_State_NS <= Output_State; 
> 
> if Output_Enable = '1' then 
> 
> case Output_State is 
> 
> when State_a => 
> A_O <= '1'; 
> 
> B_O <= '1'; 
> 
> if Condition_A then 
> 
> Output_State_NS <= State_b; 
> 
> end if; 
> 
> when State\_b => 
> ... 
> 
> end case; 
> 
> end if; 
> end process; 
> 
> on clock 1 both Output_Enable and Condition_A = '1', on clock 2, Output_Enable = '0'; In my ModelSim simulation the Output_State is at State_a, not at State_b on clock 2. 
> 
> Why is it not at State_b? 
> 
> Thank you. 
> 
> Weng

Hi,

I have found an error at another place and the listed code is right.

Weng