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Is there any software I can use to transform state machines in VHDL into drawings?

Started by Tianxiang Weng September 8, 2021
Hi,
I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings.

Is there any software I can use to transform state machines in VHDL into drawings?

Thank you.

Weng

On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote:
> Hi, > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. > > Is there any software I can use to transform state machines in VHDL into drawings? > > Thank you. > > Weng
Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes.
On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:
> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote=
:=20
> > Hi,=20 > > I have designed many state machines in VHDL, and I hope to use any soft=
ware to transform the state machines in VHDL into drawings.=20
> >=20 > > Is there any software I can use to transform state machines in VHDL int=
o drawings?=20
> >=20 > > Thank you.=20 > >=20 > > Weng > Questasim has a FSM debugger option that generates a graphical view of yo=
ur state machine, but it's not always a great view for documentation purpos= es. What I have been developing is a set of new hardware circuits that have bee= n never used. I want to apply for patents with full state machines design d= isclosed. For correctness, the state machines block diagrams should be cons= istent with the source code in VHDL. So I am seeking such tools. Now I have= to draw block diagrams manually, it may introduce inconsistence. Weng
Tianxiang Weng <wtxwtx@gmail.com> schrieb:
> On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote: >> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wrote: >> > Hi, >> > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. >> > >> > Is there any software I can use to transform state machines in VHDL into drawings? >> > >> > Thank you. >> > >> > Weng >> Questasim has a FSM debugger option that generates a graphical view of your state machine, but it's not always a great view for documentation purposes. > > What I have been developing is a set of new hardware circuits that have been never used. I want to apply for patents with full state machines design disclosed. For correctness, the state machines block diagrams should be consistent with the source code in VHDL. So I am seeking such tools. Now I have to draw block diagrams manually, it may introduce inconsistence.
You could use https://github.com/hneemann/Digital to draw your state machines, then export to VHDL.
On Friday, September 10, 2021 at 3:24:05 AM UTC-7, Thomas Koenig wrote:
> Tianxiang Weng <wtx...@gmail.com> schrieb: > > On Thursday, September 9, 2021 at 8:01:46 AM UTC-7, kkoorndyk wrote:=20 > >> On Wednesday, September 8, 2021 at 4:24:49 PM UTC-4, Tianxiang Weng wr=
ote:=20
> >> > Hi,=20 > >> > I have designed many state machines in VHDL, and I hope to use any s=
oftware to transform the state machines in VHDL into drawings.=20
> >> >=20 > >> > Is there any software I can use to transform state machines in VHDL =
into drawings?=20
> >> >=20 > >> > Thank you.=20 > >> >=20 > >> > Weng=20 > >> Questasim has a FSM debugger option that generates a graphical view of=
your state machine, but it's not always a great view for documentation pur= poses.=20
> >=20 > > What I have been developing is a set of new hardware circuits that have=
been never used. I want to apply for patents with full state machines desi= gn disclosed. For correctness, the state machines block diagrams should be = consistent with the source code in VHDL. So I am seeking such tools. Now I = have to draw block diagrams manually, it may introduce inconsistency.
> You could use https://github.com/hneemann/Digital to draw your state=20 > machines, then export to VHDL.
Thomas Koenig, I reviewed the website https://github.com/hneemann/Digital; it is a wonderf= ul product, but I prefer my coding practice: using VHDL and drawing mutuall= y to complete a complex state machine. I use Intel Visio to draw state mach= ine block diagrams.=20 When reviewing a state machine design, it is easier to use state machine bl= ock diagrams.=20 Thank you. Weng
Tianxiang Weng <wtxwtx@gmail.com> wrote:
> When reviewing a state machine design, it is easier to use state machine > block diagrams.
A codebase I look after puts $display statements in the code that print Graphviz code for each state in the state machine. The testbench exercises the code to pass through all the states. When run, you pipe the output into a .dot file and feed that into Graphviz, which will generate a PNG, SVG, PDF of the state transition diagram. It's a hack, but it works well enough. Theo
I believe the Sigasi editor has something like that: https://insights.sigasi.com/manual/views/#state-machine-view

Cheers,
Guy.

On Wednesday, September 8, 2021 at 10:24:49 PM UTC+2, Tianxiang Weng wrote:
> Hi, > I have designed many state machines in VHDL, and I hope to use any software to transform the state machines in VHDL into drawings. > > Is there any software I can use to transform state machines in VHDL into drawings? > > Thank you. > > Weng
TerosHDL plugin in VSCode has some rudimentary state-machine detection