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Good day gents,
I am wondering if VHDL (or Verilog) code exists =
in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric =
duty cycle.
Below some code can be found which generates a by-2 multiplied frequency =
- however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
-- Frequency Doubler using DFF
-- code in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo =3D 2*fi
end F2;
architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;
begin
process (clk) begin
if (clk 'event and clk =3D '1') then
q <=3D notq;
end if;
end process;
notq <=3D not q ;
clk <=3D (notq xnor fi) ;
fo <=3D clk;
end behav;
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</HEAD>
<BODY bgColor=3D#ffffff>
<DIV><FONT face=3DArial size=3D2>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Good day =
gents,</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM> =20
=
=20
I am wondering if VHDL (or Verilog) code exists in =
order to=20
make a frequency doubler in a normal</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>CPLD (without=20
internal DDL/DPL/PLL infrastructure ) with a symmetric duty=20
cycle.</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Below some code can =
be found=20
which generates a by-2 multiplied frequency - however the duty=20
cycle</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>is very =
assymmetrical=20
...</EM></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Many thanks for =
your input=20
!</EM></FONT></DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></EM> </DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2>Regards,</FONT></EM></DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></EM> </DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2>Michel</FONT></EM></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><EM><FONT color=3D#ff0000>-- Frequency =
Doubler using=20
DFF<BR>-- code in VHDL<BR></FONT></EM></DIV></FONT><FONT face=3DArial=20
size=3D2></FONT>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>library =
ieee;<BR>use=20
ieee.std_logic_1164.all;</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff =
size=3D2><EM></EM></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>entity F2 =
is<BR>port (fi :=20
in std_logic; -- Input signal=20
fi<BR> fo : out=20
std_logic); -- fo =3D 2*fi<BR>end F2;</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff =
size=3D2><EM></EM></FONT> </DIV><FONT=20
face=3DArial size=3D2>
<DIV><BR><FONT color=3D#0000ff><EM>architecture behav of F2 is<BR>signal =
clk : std_logic;<BR>signal q :  =
;std_logic;<BR>signal notq : std_logic;</EM></FONT><=
/DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><BR><FONT color=3D#0000ff><EM>begin<BR>process (clk) =
begin<BR> if (clk=20
'event and clk =3D '1') then<BR> q <=3D notq;<BR> end =
if;<BR>end=20
process;</EM></FONT></DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><FONT color=3D#0000ff><EM>notq <=3D not q ;<BR>clk <=3D (notq =
xnor fi)=20
;<BR>fo <=3D clk;</EM></FONT></DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><FONT color=3D#0000ff><EM>end=20
behav;</EM></FONT></FONT></DIV></FONT></DIV></BODY></HTML>
------=_NextPart_000_0029_01C3A95C.F07B3E80--
Frequency Doubler - VHDL/Verilog
Started by ●November 12, 2003
Reply by ●November 12, 20032003-11-12
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You can't make a symmetric-duty-cycle frequency doubler in digital logic =
unless you have a precisely controlled delay element.
-Kevin
"Gazelle" <wmu@pandora.be> wrote in message =
news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code =
exists in order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric =
duty cycle.
Below some code can be found which generates a by-2 multiplied =
frequency - however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
-- Frequency Doubler using DFF
-- code in VHDL
library ieee;
use ieee.std_logic_1164.all;
entity F2 is
port (fi : in std_logic; -- Input signal fi
fo : out std_logic); -- fo =3D 2*fi
end F2;
architecture behav of F2 is
signal clk : std_logic;
signal q : std_logic;
signal notq : std_logic;
begin
process (clk) begin
if (clk 'event and clk =3D '1') then
q <=3D notq;
end if;
end process;
notq <=3D not q ;
clk <=3D (notq xnor fi) ;
fo <=3D clk;
end behav;
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<DIV><FONT face=3DArial size=3D2>You can't make a symmetric-duty-cycle =
frequency=20
doubler in digital logic unless you have a precisely controlled delay=20
element.</FONT></DIV>
<DIV><FONT face=3DArial size=3D2>-Kevin</FONT></DIV>
<BLOCKQUOTE dir=3Dltr=20
style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; =
BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px">
<DIV>"Gazelle" <<A =
href=3D"mailto:wmu@pandora.be">wmu@pandora.be</A>>=20
wrote in message <A=20
=
href=3D"news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be">news:S_vsb.200=
88$Q87.707719@phobos.telenet-ops.be</A>...</DIV>
<DIV><FONT face=3DArial size=3D2>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Good day=20
gents,</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff =
size=3D2><EM> =20
=
=20
I am wondering if VHDL (or Verilog) code exists in =
order to=20
make a frequency doubler in a normal</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>CPLD (without=20
internal DDL/DPL/PLL infrastructure ) with a symmetric duty=20
cycle.</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Below some code =
can be found=20
which generates a by-2 multiplied frequency - however the duty=20
cycle</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>is very =
assymmetrical=20
...</EM></FONT></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Many thanks for =
your input=20
!</EM></FONT></DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></EM> </DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2>Regards,</FONT></EM></DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2></FONT></EM> </DIV>
<DIV><EM><FONT face=3DArial color=3D#0000ff =
size=3D2>Michel</FONT></EM></DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2></FONT> </DIV>
<DIV><FONT face=3DArial size=3D2><EM><FONT color=3D#ff0000>-- =
Frequency Doubler=20
using DFF<BR>-- code in VHDL<BR></FONT></EM></DIV></FONT><FONT =
face=3DArial=20
size=3D2></FONT>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>library =
ieee;<BR>use=20
ieee.std_logic_1164.all;</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff =
size=3D2><EM></EM></FONT> </DIV>
<DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>entity F2 =
is<BR>port (fi=20
: in std_logic; -- Input signal=20
fi<BR> fo : out=20
std_logic); -- fo =3D 2*fi<BR>end F2;</EM></FONT></DIV>
<DIV><FONT face=3DArial color=3D#0000ff =
size=3D2><EM></EM></FONT> </DIV><FONT=20
face=3DArial size=3D2>
<DIV><BR><FONT color=3D#0000ff><EM>architecture behav of F2 =
is<BR>signal=20
=
clk : std_logic;<BR>signal q :  =
;std_logic;<BR>signal notq : std_logic;</EM></FONT><=
/DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><BR><FONT color=3D#0000ff><EM>begin<BR>process (clk) =
begin<BR> if (clk=20
'event and clk =3D '1') then<BR> q <=3D notq;<BR> end =
if;<BR>end=20
process;</EM></FONT></DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><FONT color=3D#0000ff><EM>notq <=3D not q ;<BR>clk <=3D =
(notq xnor fi)=20
;<BR>fo <=3D clk;</EM></FONT></DIV>
<DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV>
<DIV><FONT color=3D#0000ff><EM>end=20
behav;</EM></FONT></FONT></DIV></FONT></DIV></BLOCKQUOTE></BODY></HTML>
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Reply by ●November 12, 20032003-11-12
If you don't care about the 2f duty cycle, and are also willing to live with the affect of uncontrolled incoming duty cycle at f, causing alternating period length at 2f, then you can use the circuit described in TechXclusives "Six Easy Pieces". But if you need better defined timing, you need a DLL- or PLL-like structure, there is no way around that. Peter Alfke, Xilinx Applications ================> Gazelle wrote: > > Good day gents, > I am wondering if VHDL (or Verilog) code > exists in order to make a frequency doubler in a normal > CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric > duty cycle. > Below some code can be found which generates a by-2 multiplied > frequency - however the duty cycle > is very assymmetrical ... > > Many thanks for your input ! > > Regards, > > Michel > > > -- Frequency Doubler using DFF > -- code in VHDL > library ieee; > use ieee.std_logic_1164.all; > > entity F2 is > port (fi : in std_logic; -- Input signal fi > fo : out std_logic); -- fo = 2*fi > end F2; > > > architecture behav of F2 is > signal clk : std_logic; > signal q : std_logic; > signal notq : std_logic; > > > begin > process (clk) begin > if (clk 'event and clk = '1') then > q <= notq; > end if; > end process; > > notq <= not q ; > clk <= (notq xnor fi) ; > fo <= clk; > > end behav;
Reply by ●November 12, 20032003-11-12
>If you don't care about the 2f duty cycle, and are also willing to live >with the affect of uncontrolled incoming duty cycle at f, causing >alternating period length at 2f, then you can use the circuit described >in TechXclusives "Six Easy Pieces".Assuming the clock is always running and at least in the ballpark of 50-50 duty cycle... Can I fixup the duty cycle with a cap, inverter, and big feedback/bias resistor? If I'm willing to go off-chip and back in, will that work for the 2F clock? [Yes, DLLs/PLLs are good.] -- The suespammers.org mail server is located in California. So are all my other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited commercial e-mail to my suespammers.org address or any of my other addresses. These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●November 12, 20032003-11-12
Hal, I like your line or thought, and I have been thinking along the same lines, without good results. Maybe this community can come up with a simple solution: Use a few external components to adjust the duty cycle, and perhaps also the alternate period problem. For simplicity: accept a relatively low frequency ( <40 MHz). Any takers out there? I can promise publication, fame and glory... Peter Alfke ============================== Hal Murray wrote:> > >If you don't care about the 2f duty cycle, and are also willing to live > >with the affect of uncontrolled incoming duty cycle at f, causing > >alternating period length at 2f, then you can use the circuit described > >in TechXclusives "Six Easy Pieces". > > Assuming the clock is always running and at least in the ballpark of > 50-50 duty cycle... > > Can I fixup the duty cycle with a cap, inverter, and big > feedback/bias resistor? > > If I'm willing to go off-chip and back in, will that work for the > 2F clock? > > [Yes, DLLs/PLLs are good.] > > -- > The suespammers.org mail server is located in California. So are all my > other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited > commercial e-mail to my suespammers.org address or any of my other addresses. > These are my opinions, not necessarily my employer's. I hate spam.
Reply by ●November 13, 20032003-11-13
This is a multi-part message in MIME format. ------=_NextPart_000_0038_01C3AA07.97F47820 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable HI, You didn't say anything about the frequency, so maybe for lower = frequencies one way is to cascade 2 of these 2f circuits to get a 4f = frequency and then using a simple flipflop to divide it by two, get a = perfect 50% duty cycle 2f signal. Best Regards Arash "Gazelle" <wmu@pandora.be> wrote in message = news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be... Good day gents, I am wondering if VHDL (or Verilog) code = exists in order to make a frequency doubler in a normal CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric = duty cycle. Below some code can be found which generates a by-2 multiplied = frequency - however the duty cycle is very assymmetrical ... Many thanks for your input ! Regards, Michel -- Frequency Doubler using DFF -- code in VHDL library ieee; use ieee.std_logic_1164.all; entity F2 is port (fi : in std_logic; -- Input signal fi fo : out std_logic); -- fo =3D 2*fi end F2; architecture behav of F2 is signal clk : std_logic; signal q : std_logic; signal notq : std_logic; begin process (clk) begin if (clk 'event and clk =3D '1') then q <=3D notq; end if; end process; notq <=3D not q ; clk <=3D (notq xnor fi) ; fo <=3D clk; end behav; ------=_NextPart_000_0038_01C3AA07.97F47820 Content-Type: text/html; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN"> <HTML><HEAD> <META http-equiv=3DContent-Type content=3D"text/html; = charset=3Diso-8859-1"> <META content=3D"MSHTML 6.00.2800.1276" name=3DGENERATOR> <STYLE></STYLE> </HEAD> <BODY bgColor=3D#ffffff> <DIV><FONT face=3DArial size=3D2>HI,</FONT></DIV> <DIV><FONT face=3DArial size=3D2>You didn't say anything about the = frequency, so=20 maybe for lower frequencies one way is to cascade 2 of these 2f circuits = to get=20 a 4f frequency and then using a simple flipflop to divide it by two, get = a=20 perfect 50% duty cycle 2f signal.</FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2>Best Regards</FONT></DIV> <DIV><FONT face=3DArial size=3D2>Arash</FONT></DIV> <BLOCKQUOTE dir=3Dltr=20 style=3D"PADDING-RIGHT: 0px; PADDING-LEFT: 5px; MARGIN-LEFT: 5px; = BORDER-LEFT: #000000 2px solid; MARGIN-RIGHT: 0px"> <DIV>"Gazelle" <<A = href=3D"mailto:wmu@pandora.be">wmu@pandora.be</A>>=20 wrote in message <A=20 = href=3D"news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be">news:S_vsb.200= 88$Q87.707719@phobos.telenet-ops.be</A>...</DIV> <DIV><FONT face=3DArial size=3D2> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Good day=20 gents,</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff = size=3D2><EM> =20 = =20 I am wondering if VHDL (or Verilog) code exists in = order to=20 make a frequency doubler in a normal</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>CPLD (without=20 internal DDL/DPL/PLL infrastructure ) with a symmetric duty=20 cycle.</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Below some code = can be found=20 which generates a by-2 multiplied frequency - however the duty=20 cycle</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>is very = assymmetrical=20 ...</EM></FONT></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>Many thanks for = your input=20 !</EM></FONT></DIV> <DIV><EM><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></EM> </DIV> <DIV><EM><FONT face=3DArial color=3D#0000ff = size=3D2>Regards,</FONT></EM></DIV> <DIV><EM><FONT face=3DArial color=3D#0000ff = size=3D2></FONT></EM> </DIV> <DIV><EM><FONT face=3DArial color=3D#0000ff = size=3D2>Michel</FONT></EM></DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2></FONT> </DIV> <DIV><FONT face=3DArial size=3D2><EM><FONT color=3D#ff0000>-- = Frequency Doubler=20 using DFF<BR>-- code in VHDL<BR></FONT></EM></DIV></FONT><FONT = face=3DArial=20 size=3D2></FONT> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>library = ieee;<BR>use=20 ieee.std_logic_1164.all;</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff = size=3D2><EM></EM></FONT> </DIV> <DIV><FONT face=3DArial color=3D#0000ff size=3D2><EM>entity F2 = is<BR>port (fi=20 : in std_logic; -- Input signal=20 fi<BR> fo : out=20 std_logic); -- fo =3D 2*fi<BR>end F2;</EM></FONT></DIV> <DIV><FONT face=3DArial color=3D#0000ff = size=3D2><EM></EM></FONT> </DIV><FONT=20 face=3DArial size=3D2> <DIV><BR><FONT color=3D#0000ff><EM>architecture behav of F2 = is<BR>signal=20 = clk : std_logic;<BR>signal q :  = ;std_logic;<BR>signal notq : std_logic;</EM></FONT><= /DIV> <DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV> <DIV><BR><FONT color=3D#0000ff><EM>begin<BR>process (clk) = begin<BR> if (clk=20 'event and clk =3D '1') then<BR> q <=3D notq;<BR> end = if;<BR>end=20 process;</EM></FONT></DIV> <DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV> <DIV><FONT color=3D#0000ff><EM>notq <=3D not q ;<BR>clk <=3D = (notq xnor fi)=20 ;<BR>fo <=3D clk;</EM></FONT></DIV> <DIV><FONT color=3D#0000ff><EM></EM></FONT> </DIV> <DIV><FONT color=3D#0000ff><EM>end=20 behav;</EM></FONT></FONT></DIV></FONT></DIV></BLOCKQUOTE></BODY></HTML> ------=_NextPart_000_0038_01C3AA07.97F47820--
Reply by ●November 13, 20032003-11-13
Arash,
That won't work. Try drawing a timing diagram to see why!
cheers, Syms.
"Arash Salarian" <arash dot salarian at epfl dot ch> wrote in message
news:3fb3a9cf$1@epflnews.epfl.ch...
HI,
You didn't say anything about the frequency, so maybe for lower frequencies
one way is to cascade 2 of these 2f circuits to get a 4f frequency and then
using a simple flipflop to divide it by two, get a perfect 50% duty cycle 2f
signal.
Best Regards
Arash
"Gazelle" <wmu@pandora.be> wrote in message
news:S_vsb.20088$Q87.707719@phobos.telenet-ops.be...
Good day gents,
I am wondering if VHDL (or Verilog) code exists in
order to make a frequency doubler in a normal
CPLD (without internal DDL/DPL/PLL infrastructure ) with a symmetric duty
cycle.
Below some code can be found which generates a by-2 multiplied frequency -
however the duty cycle
is very assymmetrical ...
Many thanks for your input !
Regards,
Michel
Reply by ●November 13, 20032003-11-13
Doubling again and then dividing does not solve the problem. It just gets you back where you were. :-( Peter Alfke
Reply by ●November 13, 20032003-11-13
On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke <peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>:>Hal, >I like your line or thought, and I have been thinking along the same >lines, without good results. >Maybe this community can come up with a simple solution: >Use a few external components to adjust the duty cycle, and perhaps also >the alternate period problem. >For simplicity: accept a relatively low frequency ( <40 MHz). >Any takers out there? >I can promise publication, fame and glory... >Peter AlfkeWell, the analog way was to make a coil with a center tap and 2 diodes. The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz supply). This works fine for analog (amplitude modulated) signals too, I have used it a 4.43 MHz to double color subcarrier. You will have to go off FPGA, drive a small ferrite transformer, slice it with a transistor, and back into FPGA. In these days many people are paranoid about discrete components perhaps. Not to mention a coil or transformer. But it is really simple. Of cause any non-linear component (MOSFET / FET / Transistor) can be used to double frequency, just bias it in the non linear region, and put a circuit tuned to 2f in its output, 3 f and 4f also works fine. Radio stuff.
Reply by ●November 13, 20032003-11-13
Well, this only works with a tuned circuit that filters out the subharmonics. The issue with a truly digital internal solution is the sensitivity to incoming non-50% duty cycle. No transformer and rectifier alone can help there, but a tuned circuit would. But LCs are not so fashionable anymore... Peter Alfke Jan Panteltje wrote:> > On a sunny day (Wed, 12 Nov 2003 13:55:30 -0800) it happened Peter Alfke > <peter@xilinx.com> wrote in <3FB2AC53.76A5CA48@xilinx.com>: > > >Hal, > >I like your line or thought, and I have been thinking along the same > >lines, without good results. > >Maybe this community can come up with a simple solution: > >Use a few external components to adjust the duty cycle, and perhaps also > >the alternate period problem. > >For simplicity: accept a relatively low frequency ( <40 MHz). > >Any takers out there? > >I can promise publication, fame and glory... > >Peter Alfke > Well, the analog way was to make a coil with a center tap and 2 diodes. > The double phase rectified wave you get is 2f ( like 120 Hz hum from 60 Hz > supply). > This works fine for analog (amplitude modulated) signals too, I have used it > a 4.43 MHz to double color subcarrier. > You will have to go off FPGA, drive a small ferrite transformer, slice it with a > transistor, and back into FPGA. > In these days many people are paranoid about discrete components perhaps. > Not to mention a coil or transformer. > But it is really simple. > Of cause any non-linear component (MOSFET / FET / Transistor) can be used > to double frequency, just bias it in the non linear region, and put a circuit tuned to > 2f in its output, 3 f and 4f also works fine. > Radio stuff.
