rather simple gsr Q

Brian Philofsky wrote:
> Roger,
>
>     There is not a way to directly view the GSR signal within a design
> but there is a pseudo-way to get it.  If you instantiate an FD, and tie
> the input to Vcc and connect your clock, the FF will reset to zero when
> GSR is asserted and go to one the first clock cycle GSR is deasserted.
> You can invert the polarity by setting the INIT attribute to a one and
> tying a ground to the input.  You may need to place some attributes on
> the FF to make sure the tools do not optimize it away thinking it is a
> constant but in theory, that should give to a look at to when GSR is
> asserted for the rest of your design.  I would not know whey you would
> every try to build memory within and FPGA out of LUTs configured as nand
> and inv gates when you can have much more efficient use of the LUTs when
> configured as memories but to each their own.
>

I do not actually plan to build memory elements in the FPGA. I only
cited as a possible academic situation where one migth require the
FPGA's gsr signal.

In regard to your proposd idea: Great idea! It needs a clock and as
such the oscillator startup time is added to the gsr pulse, but that
does not matter. Until the clock shows up, the gsr can be asserted or
negated --> gsr being held or released will will have no impact if
there is no clock! Thx!

-Roger