humble suggestion for Xilinx

Since the max serial-slave configuration rate on things like Spartan3
chips is, what, 20 MHz or something, you might consider slowing down
the CCLK input path, and/or adding some serious hysteresis on future
parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
and stubs and vias and such, so may not be as pristine as a system
clock. CCLK seems to be every bit as touchy as main clock pins, and it
really needn't be.

John

John Larkin wrote:
> 
> Since the max serial-slave configuration rate on things like Spartan3
> chips is, what, 20 MHz or something, you might consider slowing down
> the CCLK input path, and/or adding some serious hysteresis on future
> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
> and stubs and vias and such, so may not be as pristine as a system
> clock. CCLK seems to be every bit as touchy as main clock pins, and it
> really needn't be.
> 
> John

John,

Are your suggestions for the CCLK generated by the Xilinx device or the 
CCLK received by the Xilinx device?

I think the max speed is up to 66 MHz these days in the Spartan3E.  It 
may not be LVDS rates but it's not 4000 series logic, either.

- John_H

John Larkin wrote:
> On a pcb, CCLK is often a shared SPI clock, with lots of loads
> and stubs and vias and such, so may not be as pristine as a system
> clock. CCLK seems to be every bit as touchy as main clock pins, and it
> really needn't be.
>

What it's really saying is that when designing a PCB, CCLK should be
treated with as much care and respect as any other clock signal so you
won't have lots of loads, stubs and vias and such.

KJ

On 14 Apr 2006 03:03:17 -0700, "KJ" <Kevin.Jennings@Unisys.com> wrote:

>John Larkin wrote:
>> On a pcb, CCLK is often a shared SPI clock, with lots of loads
>> and stubs and vias and such, so may not be as pristine as a system
>> clock. CCLK seems to be every bit as touchy as main clock pins, and it
>> really needn't be.
>>
>
>What it's really saying is that when designing a PCB, CCLK should be
>treated with as much care and respect as any other clock signal so you
>won't have lots of loads, stubs and vias and such.
>

And what I'm saying is that treating it as such shouldn't be
necessary. 

John

On Fri, 14 Apr 2006 05:53:30 GMT, John_H <johnhandwork@mail.com>
wrote:

>John Larkin wrote:
>> 
>> Since the max serial-slave configuration rate on things like Spartan3
>> chips is, what, 20 MHz or something, you might consider slowing down
>> the CCLK input path, and/or adding some serious hysteresis on future
>> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
>> and stubs and vias and such, so may not be as pristine as a system
>> clock. CCLK seems to be every bit as touchy as main clock pins, and it
>> really needn't be.
>> 
>> John
>
>John,
>
>Are your suggestions for the CCLK generated by the Xilinx device or the 
>CCLK received by the Xilinx device?
>

In serial-slave mode, the FPGA receives CCLK.

>I think the max speed is up to 66 MHz these days in the Spartan3E.  It 
>may not be LVDS rates but it's not 4000 series logic, either.

Right. Improving the noise immunity of the CCLK receiver would have
exactly one practical result: more FPGAs would configure.

John

John Larkin wrote:
> 
> Since the max serial-slave configuration rate on things like Spartan3
> chips is, what, 20 MHz or something, you might consider slowing down
> the CCLK input path, and/or adding some serious hysteresis on future
> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
> and stubs and vias and such, so may not be as pristine as a system
> clock. CCLK seems to be every bit as touchy as main clock pins, and it
> really needn't be.

Wouldn't one expect this to be 'normal design practise' ?

I suppose Xilinx missed that obvious feature, becasue there are no
other Schmitt cells on the die, and even tho the CPLDs have this,
I'm sure their inter-department sharing is like most large companies :)

-jg

Hi John,

Thank you for the feedback.  Fortunately, this is already a planned
enhancement on future families.

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.

On 14 Apr 2006 15:47:28 -0700, "Steve Knapp (Xilinx Spartan-3
Generation FPGAs)" <steve.knapp@xilinx.com> wrote:

>Hi John,
>
>Thank you for the feedback.  Fortunately, this is already a planned
>enhancement on future families.
>

Thank you! Thank you!

Maybe I'm not crazy after all. Maybe.

Next, how about making the real clock inputs programmable to be slower
and less noise sensitive? Yeah, some people are never satisfied.

John

On Sat, 15 Apr 2006 10:45:06 +1200, Jim Granville
<no.spam@designtools.co.nz> wrote:

>
>John Larkin wrote:
>> 
>> Since the max serial-slave configuration rate on things like Spartan3
>> chips is, what, 20 MHz or something, you might consider slowing down
>> the CCLK input path, and/or adding some serious hysteresis on future
>> parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
>> and stubs and vias and such, so may not be as pristine as a system
>> clock. CCLK seems to be every bit as touchy as main clock pins, and it
>> really needn't be.
>
>Wouldn't one expect this to be 'normal design practise' ?
>
>I suppose Xilinx missed that obvious feature, becasue there are no
>other Schmitt cells on the die, and even tho the CPLDs have this,
>I'm sure their inter-department sharing is like most large companies :)
>

I have it secondhand (one of my guys tells me) that all S3 inputs have
about 100 mV of hysteresis. But that's not enough to improve noise
immunity in most practical situations.

It's good that FPGAs keep getting faster, but not all applications
need all that speed, and pickiness about clock edge quality can be a
real liability in a lot of slower applications.

John

John Larkin wrote:
> On Sat, 15 Apr 2006 10:45:06 +1200, Jim Granville
> <no.spam@designtools.co.nz> wrote:
> 
> 
>>John Larkin wrote:
>>
>>>Since the max serial-slave configuration rate on things like Spartan3
>>>chips is, what, 20 MHz or something, you might consider slowing down
>>>the CCLK input path, and/or adding some serious hysteresis on future
>>>parts. On a pcb, CCLK is often a shared SPI clock, with lots of loads
>>>and stubs and vias and such, so may not be as pristine as a system
>>>clock. CCLK seems to be every bit as touchy as main clock pins, and it
>>>really needn't be.
>>
>>Wouldn't one expect this to be 'normal design practise' ?
>>
>>I suppose Xilinx missed that obvious feature, becasue there are no
>>other Schmitt cells on the die, and even tho the CPLDs have this,
>>I'm sure their inter-department sharing is like most large companies :)
>>
> 
> 
> I have it secondhand (one of my guys tells me) that all S3 inputs have
> about 100 mV of hysteresis. But that's not enough to improve noise
> immunity in most practical situations.
> 
> It's good that FPGAs keep getting faster, but not all applications
> need all that speed, and pickiness about clock edge quality can be a
> real liability in a lot of slower applications.

  True - there is also a slight speed penalty for the full schmitt cells,
so that's a reason why the speed-at-all-costs FPGA sector ignores the 
benefits.
  Still, the news from Steve K is good :)

-jg