driving high speed ADC using an FPGA

Hi Everyone,

I am wondering if it would be possible to drive a 800 MHz 10 bit 
parellel A/D using an FPGA which has a 100MHz system clock.

Thanks,

Sanka

Probably.  Budget also works into the decision.
Do you have your FPGA family or specific device already targeted?
Please consider driving your ADC clock from a clean source that doesn't 
include the FPGA in the path; crosstalk from other I/O "near" a clock 
generated by the FPGA will add jitter to your high speed clock that could be 
detrimental to a very high performance system.

"Sanka Piyaratna" <jayasanka.piyaratna@gmail.com> wrote in message 
news:124ar68ie11gvcb@corp.supernews.com...
> Hi Everyone,
>
> I am wondering if it would be possible to drive a 800 MHz 10 bit parellel 
> A/D using an FPGA which has a 100MHz system clock.
>
> Thanks,
>
> Sanka 

Sanka Piyaratna wrote:
> Hi Everyone,
> 
> I am wondering if it would be possible to drive a 800 MHz 10 bit 
> parellel A/D using an FPGA which has a 100MHz system clock.
> 
> Thanks,
> 
> Sanka

I'm not sure what you mean by drive the ADC with the FPGA.  The signal 
flow is the other way around: the ADC will drive the FPGA.  You should 
not drive your ADC clocks from the FPGA.  The jitter introduced by the 
FPGA will absolutely kill the noise performance of the ADC at 800MHz. 
At 100 MHz it will reduce the SNR to considerably less than the 10 bits.

Use a clean external clock to clock the ADC.  Most high speed ADCs have 
a clock output that can be fed to the FPGA to get a clean transfer of 
the ADC data into the FPGA.

As Andraka pointed out, I guess you want your ADC Ouput connected to
the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz
and you want the process those samples in your FPGA which can only work
at the max of 100 Mhz clock, the only way to do that is to use a DMUX
chip prior to the FPGA on board. There are DMUX chips available that
will demux 1:4 or 1:8 which also gives the slowed down data latch
signals (clock) which can be used as clock to latch the demux data
inside the FPGA. 

Hope this helps.

Venkat.

Thank you very much everyone for your help. I was originally thinking of 
the problem in the wrong way around. Now I understand what you mean. I 
have not yet determined what parts to use. At this stage I am still 
scoping the problem.

Thank you,

Sanka

Venkat wrote:
> As Andraka pointed out, I guess you want your ADC Ouput connected to
> the FPGA and if from what you mean the ADC is gonna sample at 800 Mhz
> and you want the process those samples in your FPGA which can only work
> at the max of 100 Mhz clock, the only way to do that is to use a DMUX
> chip prior to the FPGA on board. There are DMUX chips available that
> will demux 1:4 or 1:8 which also gives the slowed down data latch
> signals (clock) which can be used as clock to latch the demux data
> inside the FPGA. 
> 
> Hope this helps.
> 
> Venkat.
>