-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1 Does anybody know if the Xilinx PCI Express cores from Xilinx can run w/ Icarus Verilog? I can't seem to get access to an eval copy to find out for myself. The link to the .tar.gz (and the .zip) seem dead for me. Nor can I find out if I can use it with WebPACK or I need the full ISE to access the actual Verilog. The last full ISE I have is 6.2, but I can obviously get at WebPACK releases. Does WebPACK have the CORE generators I'd need? - -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.2.5 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iD8DBQFER77GrPt1Sc2b3ikRAinfAJ9oG/ezCM4X3fhgUkTTnMdAJqhD5gCfZ+MH BlApRFl0pMe8P2x5TCfhnPE= =/YoG -----END PGP SIGNATURE-----
Xilinx PCIe core vs. Icarus Verilog
Started by ●April 20, 2006
Reply by ●April 21, 20062006-04-21
Stephen Williams wrote:> -----BEGIN PGP SIGNED MESSAGE----- > Hash: SHA1 > > > Does anybody know if the Xilinx PCI Express cores from Xilinx can > run w/ Icarus Verilog? I can't seem to get access to an eval copy > to find out for myself. The link to the .tar.gz (and the .zip) seem > dead for me. > > Nor can I find out if I can use it with WebPACK or I need the full > ISE to access the actual Verilog. The last full ISE I have is 6.2, > but I can obviously get at WebPACK releases. Does WebPACK have the > CORE generators I'd need? > - -- > Steve Williams "The woods are lovely, dark and deep. > steve at icarus.com But I have promises to keep, > http://www.icarus.com and lines to code before I sleep, > http://www.picturel.com And lines to code before I sleep." > -----BEGIN PGP SIGNATURE----- > Version: GnuPG v1.2.5 (GNU/Linux) > Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org > > iD8DBQFER77GrPt1Sc2b3ikRAinfAJ9oG/ezCM4X3fhgUkTTnMdAJqhD5gCfZ+MH > BlApRFl0pMe8P2x5TCfhnPE= > =/YoG > -----END PGP SIGNATURE-----"Xilinx provides you with the ability to evaluate the functionality of PCI Express 1, 4 & 8 Lane Endpoint cores using MTI precompiled functional simulation models." You don't get access to the Verilog. And it's unclear if you get the RTL for the purchased version either. (One didn't for the PCI core.) You can understand that Xilinx would lock it to their part.
Reply by ●April 21, 20062006-04-21