Hi All, <p>I am looking for documentation on <BR> estimation of FPGA device utilization from a high level design specification(idea). Can anybody tell me where I can find out this kind of document which gives idea about how to do rough estimate of gate count(ASIC) or device utilization from a high level design description. The design will ofcourse be made in VHDL/Verilog.
FPGA Device Utilization
Started by ●November 14, 2003