Spartan 3 documentation confusing...

I still have not completely figured out the pull up resistors on the
Spartan 3 chips.  It would appear that the data sheet has never been
thoroughly reviewed for omissions and errors.  Some of the information
that should be clearly indicated in any number of places is missing
and/or misleading.

"A Low logic level on HSWAP_EN activates the pull-up resistors on all
I/Os during configuration."  Does this include the dedicated
configuration signals?  How about the dual purpose configuration pins?
Or is it just the User IO?

I found this sentance to be especially unenlightening...

"The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
pull-up resistor to HSWAP_EN during configuration, regardless of the
value on the HSWAP_EN pin."

What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
(or need) a pull up to any value since it is a full time output?

Why does Xilinx make it so hard to get the all important details on a
part that has been in full production for so long?  They just updated
the Spartan 3 data sheet this month!  Why wasn't the information that
they know is lacking included?  I say they know info is lacking because
you can find it in an answer record if you know to look for it.

I may put up a web page detailing all the short comings in the Spartan
3 devices and documentation.

Rick,

Why not just email all of this to Steve Knapp directly?  Or me or Peter 
for Virtex parts?

Seems that if you'd like to help us by pointing out anything confusing 
or inconsistent, you could get it to the right party in one step.

I agree with you that answers should be scrubbed for any update to a 
document.  It is the little things that drive us all crazy.

Austin


rickman wrote:
> I still have not completely figured out the pull up resistors on the
> Spartan 3 chips.  It would appear that the data sheet has never been
> thoroughly reviewed for omissions and errors.  Some of the information
> that should be clearly indicated in any number of places is missing
> and/or misleading.
> 
> "A Low logic level on HSWAP_EN activates the pull-up resistors on all
> I/Os during configuration."  Does this include the dedicated
> configuration signals?  How about the dual purpose configuration pins?
> Or is it just the User IO?
> 
> I found this sentance to be especially unenlightening...
> 
> "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
> HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
> pull-up resistor to HSWAP_EN during configuration, regardless of the
> value on the HSWAP_EN pin."
> 
> What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
> (or need) a pull up to any value since it is a full time output?
> 
> Why does Xilinx make it so hard to get the all important details on a
> part that has been in full production for so long?  They just updated
> the Spartan 3 data sheet this month!  Why wasn't the information that
> they know is lacking included?  I say they know info is lacking because
> you can find it in an answer record if you know to look for it.
> 
> I may put up a web page detailing all the short comings in the Spartan
> 3 devices and documentation.
> 

I *didn't* address the message to anyone at Xilinx.  This was an open
message to everyone who uses Xilinx parts and might have something to
comment about it.  If you review the other thread on the documentation
shortcomings of the Spartan 3 parts, you will see that at least one
poster has encountered such signficantly difficult to resolve issues
that they consider the solution to be proprietary information.

You are a big proponent of how good a job Xilinx does on support.
Instead of asking why I posted the message, have you considered asking
why a significant issue such as 1 kohm pullup resistors on the
configuration pins remains largely undocumented?  It was only after I
found that confusing sentence shown below that I realized that these
resistors are also on the JTAG pins.  I have been asked repeatedly why
I did not use a pull down resistor on JTAG my board like the other
designs here use.  My answer was that this is what I am used to using.
I nearly changed the design since I had no strong conviction either
way.  Now I realize that if I had used a pull down of typical 1 to 4.7
kohms, the circuit would not have worked at all being biased in an
undefined region.

Come on Austin.  Don't shoot the messenger!  Listen to the message and
work on your internal processes.  If it was important enough to create
an answer record and was not in the data sheet, someone should have
made sure that it found its way into the data sheet in a clear and
accessible manner.

BTW, I still don't know if the configuration pullup resistors are
disabled by the HSWAP_EN signal.  Anyone out there know the answer?  I
really don't know if Xilinx does.  I would love to see a clear and
comprehensive table covering all the pins.



Austin Lesea wrote:
> Rick,
>
> Why not just email all of this to Steve Knapp directly?  Or me or Peter
> for Virtex parts?
>
> Seems that if you'd like to help us by pointing out anything confusing
> or inconsistent, you could get it to the right party in one step.
>
> I agree with you that answers should be scrubbed for any update to a
> document.  It is the little things that drive us all crazy.
>
> Austin
>
>
> rickman wrote:
> > I still have not completely figured out the pull up resistors on the
> > Spartan 3 chips.  It would appear that the data sheet has never been
> > thoroughly reviewed for omissions and errors.  Some of the information
> > that should be clearly indicated in any number of places is missing
> > and/or misleading.
> >
> > "A Low logic level on HSWAP_EN activates the pull-up resistors on all
> > I/Os during configuration."  Does this include the dedicated
> > configuration signals?  How about the dual purpose configuration pins?
> > Or is it just the User IO?
> >
> > I found this sentance to be especially unenlightening...
> >
> > "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
> > HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
> > pull-up resistor to HSWAP_EN during configuration, regardless of the
> > value on the HSWAP_EN pin."
> >
> > What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
> > (or need) a pull up to any value since it is a full time output?
> >
> > Why does Xilinx make it so hard to get the all important details on a
> > part that has been in full production for so long?  They just updated
> > the Spartan 3 data sheet this month!  Why wasn't the information that
> > they know is lacking included?  I say they know info is lacking because
> > you can find it in an answer record if you know to look for it.
> >
> > I may put up a web page detailing all the short comings in the Spartan
> > 3 devices and documentation.
> >

Rick!

Back off -- I am on your side.

I am just asking that you send comments to the appropriate person in 
Xilinx (too).

Go ahead and post (it is your time, and your effort).  I don't have a 
problem with that.  But, if you post something that can be fixed, at 
least give us the oppostunity to fix it.  If we screw up, then OK, 
scream and rant, and do whatever makes you feel better.

Its a big company, with many products, and millions (literally) words of 
documentation.

I didn't say we were perfect.  In fact I said we were imperfect, and 
looking for ways to get better.

I have spent about two hours today trying to identify where in the 
process APD and GPD could do better.  I am still trying to find the best 
way to attack the problems, and provide the best solutions.  It has long 
been an issue with me that tech answers should automatically feed back 
into documents, and then have a sunset so they go away after a suitable 
time when the docs now have the info (OK to have both for awhile).

That is my job (as a principal engineer) here at Xilinx:  to be an agent 
for change (for the better).  It is in my job description.

So, I really appreciate that you post (it directly helps me to fufill my 
job responsibilities), but if I don't have to go to the newsgroup to 
read it, it makes it even easier for me.  OK if you don't.  I am just 
asking (nicely).

Thanks for today's tough task, by the way.

As for "the answer" I can't do that in Spartan land, as I have no easy 
access to the chip schematics like I do for Virtex.  If it was Virtex 
X+1, I just go to the schematics and dig for awhile.  Sorry I can't do 
that for you on this one,

Austin

"rickman" <spamgoeshere4@yahoo.com> schrieb im Newsbeitrag 
news:1145896022.809609.5340@t31g2000cwb.googlegroups.com...
>I still have not completely figured out the pull up resistors on the
> Spartan 3 chips.  It would appear that the data sheet has never been
> thoroughly reviewed for omissions and errors.  Some of the information
> that should be clearly indicated in any number of places is missing
> and/or misleading.
>
> "A Low logic level on HSWAP_EN activates the pull-up resistors on all
> I/Os during configuration."  Does this include the dedicated
> configuration signals?  How about the dual purpose configuration pins?
> Or is it just the User IO?
>
> I found this sentance to be especially unenlightening...
>
> "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
> HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
> pull-up resistor to HSWAP_EN during configuration, regardless of the
> value on the HSWAP_EN pin."
>
> What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
> (or need) a pull up to any value since it is a full time output?
>
> Why does Xilinx make it so hard to get the all important details on a
> part that has been in full production for so long?  They just updated
> the Spartan 3 data sheet this month!  Why wasn't the information that
> they know is lacking included?  I say they know info is lacking because
> you can find it in an answer record if you know to look for it.
>
> I may put up a web page detailing all the short comings in the Spartan
> 3 devices and documentation.
>
Rick

TDO is not is not full-time output (or  at least doesnt have to be) TDO is 
driven when JTAG TAP is in 'shift'  states and tri-stated otherwise so a 
pullup makes sense :)

Antti

I found the missing info.  Instead of putting the details along with
the other details in the pin descriptions, the pull ups are mentioned
in the section header which I did not read.  That seems to be the only
info in the section header, the pull ups.  The pins I was researching
were on the following page and so the header was not apparent.

The confusing sentance still stands however.  Whatever the words mean,
I assume it is simply saying that there are pull up resistors on all of
the configuration pins regardless of the state of the HSWAP_EN pin.

I don't know what to make of you Austin.  You certainly don't come
across as a people person.  But thanks for the permission to post here.
 ;^)

Just FYI, I have to fight just as hard in the company where I work to
get people to produce decent documentation.  It's not that it should
always be perfect... we're all human.  But so many people don't feel
documentation matters much.  They think it is all about the product.
But people's lives depend on our products and I am taking that very
seriously.

As to this issue, it almost cost me a pointless board spin; not life
threatening, but certainly that could be career threatening.

As to contacting Steve, I have done that.  I hope that the pull up
issue becomes more widely understood.  The combination of poorly
documented pull ups and the stiff value of these pull ups in the
Spartan 3 devices can make a lot of trouble for a lot of designs.

Rick,

Well, I hope you keep up the comments.

I am seriously trying to improve the documentaion process.

If we explain it right the first time, we get less confusion, and we get 
to market faster.

Really very simple, and very self serving:  the better the docs, the 
less time wasted, and the faster our customers either gain success, or 
fail.  The faster money changes hands.  The faster we succeed (or fail 
to succeeed).

It is so simple, yet so many (most) companies get it wrong.

Just make it simple to succeed, and don't get in the way, or make things 
any tougher than they already are.

As for my personality, my wife thinks I am completely impossible ('how 
can anyone work for you?').  My staff thinks I am the best boss they 
every had ('how can your boss deal with you?').  My supervisors love 
that I always come to them with a solution to the problem ('how do you 
keep your people so happy?').  My (totally grown) kids claim I am 
totally mad, and can not be trusted even for a moment ('that's not 
fair!').  My grandchildren sense I can be completely trusted to see to 
their well being and happiness (which I can be).

So, I have a personality:  guilty as charged.  Member of the human race.

Austin

As long as you brought up your personality, I'll just say that I
remember reading about someone who reminds me of you, Napoleon.  He
thought a lot of himself too.

Austin Lesea wrote:
> Rick,
>
> Well, I hope you keep up the comments.
>
> I am seriously trying to improve the documentaion process.
>
> If we explain it right the first time, we get less confusion, and we get
> to market faster.
>
> Really very simple, and very self serving:  the better the docs, the
> less time wasted, and the faster our customers either gain success, or
> fail.  The faster money changes hands.  The faster we succeed (or fail
> to succeeed).
>
> It is so simple, yet so many (most) companies get it wrong.
>
> Just make it simple to succeed, and don't get in the way, or make things
> any tougher than they already are.
>
> As for my personality, my wife thinks I am completely impossible ('how
> can anyone work for you?').  My staff thinks I am the best boss they
> every had ('how can your boss deal with you?').  My supervisors love
> that I always come to them with a solution to the problem ('how do you
> keep your people so happy?').  My (totally grown) kids claim I am
> totally mad, and can not be trusted even for a moment ('that's not
> fair!').  My grandchildren sense I can be completely trusted to see to
> their well being and happiness (which I can be).
>
> So, I have a personality:  guilty as charged.  Member of the human race.
> 
> Austin

Rick,

Thanks for the compliment.

Austin

rickman wrote:

> As long as you brought up your personality, I'll just say that I
> remember reading about someone who reminds me of you, Napoleon.  He
> thought a lot of himself too.
> 
> Austin Lesea wrote:
> 
>>Rick,
>>
>>Well, I hope you keep up the comments.
>>
>>I am seriously trying to improve the documentaion process.
>>
>>If we explain it right the first time, we get less confusion, and we get
>>to market faster.
>>
>>Really very simple, and very self serving:  the better the docs, the
>>less time wasted, and the faster our customers either gain success, or
>>fail.  The faster money changes hands.  The faster we succeed (or fail
>>to succeeed).
>>
>>It is so simple, yet so many (most) companies get it wrong.
>>
>>Just make it simple to succeed, and don't get in the way, or make things
>>any tougher than they already are.
>>
>>As for my personality, my wife thinks I am completely impossible ('how
>>can anyone work for you?').  My staff thinks I am the best boss they
>>every had ('how can your boss deal with you?').  My supervisors love
>>that I always come to them with a solution to the problem ('how do you
>>keep your people so happy?').  My (totally grown) kids claim I am
>>totally mad, and can not be trusted even for a moment ('that's not
>>fair!').  My grandchildren sense I can be completely trusted to see to
>>their well being and happiness (which I can be).
>>
>>So, I have a personality:  guilty as charged.  Member of the human race.
>>
>>Austin
> 
> 

rickman wrote:

[... snip ...]

> "A Low logic level on HSWAP_EN activates the pull-up resistors on all
> I/Os during configuration."  Does this include the dedicated
> configuration signals?  How about the dual purpose configuration pins?
> Or is it just the User IO?

First, some background.  On Spartan-3, the dedicated configuration
pins, like CCLK, DONE, PROG_B, M2, M1, M0, and HSWAP_EN itself, all
have an internal pull-up resistor to VCCAUX that is active during
configuration, regardless of HSWAP_EN.  After configuration, these pins
have a bitstream generator option that defines their respective
behavior.

All other pins have optional pull-up resistors, controlled by the
HSWAP_EN pin.  When HSWAP_EN=0, these pull-ups are enabled to their
respective I/O Bank voltage supply (such as VCCO_0, VCCO_1, etc.).

> I found this sentance to be especially unenlightening...
>
> "The Dedicated configuration pins (CCLK, DONE, PROG_B, M2, M1, M0,
> HSWAP_EN) and the JTAG pins (TDI, TMS, TCK, and TDO) always have a
> pull-up resistor to HSWAP_EN during configuration, regardless of the
> value on the HSWAP_EN pin."
>
> What does a "pull-up resistor to HSWAP_EN" mean???  Why would TDO have
> (or need) a pull up to any value since it is a full time output?

What the who!?!  I think the intention was that the "pull-up resistor
connects to VCCAUX", _not_ HSWAP_EN.  I'll see that we get that one
fixed ASAP!

> Why does Xilinx make it so hard to get the all important details on a
> part that has been in full production for so long?  They just updated
> the Spartan 3 data sheet this month!  Why wasn't the information that
> they know is lacking included?  I say they know info is lacking because
> you can find it in an answer record if you know to look for it.

The updates happen periodically.  As various issues are reported by the
Xilinx Technical Support team, we update the documentation to make sure
that you don't bump into any known landmines (okay, not a Marketing
term).  The latest updated changed maybe 0.1% of the verbage.  We
incorporate the latest learning, new ideas, and latest information.
Believe me, we want to make your design experience as pleasant and
trouble-free as possible.

I encourage active feedback.  If something is confusing, please let us
know, as it will likely be confusing to others.  Most of our best
product and documentation ideas come from Xilinx users!  Feel free to
E-mail me directly for Spartan documentation or use the Feedback link
from the Xilinx web site.
http://www.xilinx.com/askx/feedback.htm

---------------------------------
Steven K. Knapp
Applications Manager, Xilinx Inc.
General Products Division
Spartan-3/-3E FPGAs
http://www.xilinx.com/spartan3e
E-mail: steve.knapp@xilinx.com
---------------------------------
The Spartan(tm)-3 Generation:  The World's Lowest-Cost FPGAs.