Pull up resistors on Spartan 3 mode pins

People here are driving me crazy insisting that the Xilinx factory has
told them that you *MUST* tie the mode pins to either Vaux or GND.
After finding all the info in the data sheet and talking with support,
it looks pretty clear to me that the S3 parts have a very stiff
internal pull up and there is no need for an external pull up of any
kind, resistor or direct connection to Vaux.

Am I misunderstanding?  Why did the factory tell us before that the
mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
saying?

I promise this is the last time I will ask about this.  I am totally
sick of going around this loop with everyone here.

by stiff mean smaller pullup value than 47-100kohm?

if that so then its something that is not well known - ASFAIK no FPGA
have stiff pull's before (or after configuration).

Antti

"Antti" <Antti.Lukats@xilant.com> wrote in message 
news:1146249613.640327.248660@e56g2000cwe.googlegroups.com...
> by stiff mean smaller pullup value than 47-100kohm?
>
> if that so then its something that is not well known - ASFAIK no FPGA
> have stiff pull's before (or after configuration).
>
> Antti

Antti,

Read the Spartan-3 data sheet.  It's been known to many engineers for quite 
some time that user-definable pullup and pulldown resistors are much stiffer 
than other gens.  Spartan3E "fixed" those excessive values, returning to 
something more moderate.

I just wish *I* had an answer for rickman.

- John_H 

what you mean by 'user-defineable' rickman was talking about
'pre-configuration' mode pull-ups and those can not be user defined?

Antti

I think Steve Knapp explained:
The "weak" pull-ups got too strong in S3, but they are now again made
properly in S3E.
Some people in Xilinx are overly concerned about the weakness, and thus
the danger of crosstalk into these pins.
Sometimes this paranoia leads to strong statements like "must".

BTW, it is very easy to measure the resistor value: just short-circuit
the pin to ground with a multi-meter.

With lower supply voltages, lower thresholds and sometimes higher
leakage currents, we all have to get away from the idea of 50 to 100k
resistors.1k to 3.3 k are more meaningful values for external resistors
that are supposed to define a level (unless it would affect power in
ultre-low power designs)
PeterAlfke, Xilinx

rickman wrote:

> People here are driving me crazy insisting that the Xilinx factory has
> told them that you *MUST* tie the mode pins to either Vaux or GND.
> After finding all the info in the data sheet and talking with support,
> it looks pretty clear to me that the S3 parts have a very stiff
> internal pull up and there is no need for an external pull up of any
> kind, resistor or direct connection to Vaux.
> 
> Am I misunderstanding?  Why did the factory tell us before that the
> mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
> saying?
> 
> I promise this is the last time I will ask about this.  I am totally
> sick of going around this loop with everyone here.

Design the PCB with options for SMD resistors, that can also be
0-Ohm shunts, and say 'define in production for valid logic levels'.
That gets you past the design review, and closes the case :)

-jg

Jim Granville wrote:
> rickman wrote:
>
> > People here are driving me crazy insisting that the Xilinx factory has
> > told them that you *MUST* tie the mode pins to either Vaux or GND.
> > After finding all the info in the data sheet and talking with support,
> > it looks pretty clear to me that the S3 parts have a very stiff
> > internal pull up and there is no need for an external pull up of any
> > kind, resistor or direct connection to Vaux.
> >
> > Am I misunderstanding?  Why did the factory tell us before that the
> > mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
> > saying?
> >
> > I promise this is the last time I will ask about this.  I am totally
> > sick of going around this loop with everyone here.
>
> Design the PCB with options for SMD resistors, that can also be
> 0-Ohm shunts, and say 'define in production for valid logic levels'.
> That gets you past the design review, and closes the case :)

I started the design review process with pullups and pull downs of 10
kohms and was told I had to use direct connections.  Of course they
could have been replaced with 0 ohm resistors at any time if needed.
Once I had researched the issue, I thought I had an FAE's blessing of
4.7 kohm resistors.  I had found that the pull up resistors were rather
strong in the S3 parts, but did not find any indication that there were
internal pullups on those pins.  Turns out I had missed the sentance
that told about them.  Once I found that, it all started to make sense.
 With internal pullups of 1-3 kohms I can see where a pull down
resistor would have to be low enough that there would not be much point
of using a value larger than 0 ohms.  Being very cramped for space,
especially in the area of the mode pins, I removed the pullups all
together and am relying on the internal pullups.  But some people here
("here" my work, not "here" the newsgroup) just won't let go of the
bone.  They are insisting that the pins must be connected to Vaux
directly because of what they were told a year ago.

I don't want to put parts on the board that aren't required.  It seems
pretty durn clear to me that pullup resistors are not needed on the
mode pins at any time, under any circumstances.  The board is due to
come out of layout in a couple of days and I don't want to interrupt
progress.  I don't understand why I can't get a clear answer to this
question.  Peter replied, but didn't answer the question.  I honestly
do not trust the support phone line (because I don't actually talk to
the person who gives the answer, just the gopher who relays the
message) and can't document what I am told verbally.  I can't get an
account to work to get support by email.  So I guess I'll have to
resort to working with the FAE who has already given me bad advice.

Jim Granville wrote:
> rickman wrote:
>
> > People here are driving me crazy insisting that the Xilinx factory has
> > told them that you *MUST* tie the mode pins to either Vaux or GND.
> > After finding all the info in the data sheet and talking with support,
> > it looks pretty clear to me that the S3 parts have a very stiff
> > internal pull up and there is no need for an external pull up of any
> > kind, resistor or direct connection to Vaux.
> >
> > Am I misunderstanding?  Why did the factory tell us before that the
> > mode pins *MUST* be tied to Vaux?  Did we misunderstand what they were
> > saying?
> >
> > I promise this is the last time I will ask about this.  I am totally
> > sick of going around this loop with everyone here.
>
> Design the PCB with options for SMD resistors, that can also be
> 0-Ohm shunts, and say 'define in production for valid logic levels'.
> That gets you past the design review, and closes the case :)

I started the design review process with pullups and pull downs of 10
kohms and was told I had to use direct connections.  Of course they
could have been replaced with 0 ohm resistors at any time if needed.
Once I had researched the issue, I thought I had an FAE's blessing of
4.7 kohm resistors.  I had found that the pull up resistors were rather
strong in the S3 parts, but did not find any indication that there were
internal pullups on those pins.  Turns out I had missed the sentance
that told about them.  Once I found that, it all started to make sense.
 With internal pullups of 1-3 kohms I can see where a pull down
resistor would have to be low enough that there would not be much point
of using a value larger than 0 ohms.  Being very cramped for space,
especially in the area of the mode pins, I removed the pullups all
together and am relying on the internal pullups.  But some people here
("here" my work, not "here" the newsgroup) just won't let go of the
bone.  They are insisting that the pins must be connected to Vaux
directly because of what they were told a year ago.

I don't want to put parts on the board that aren't required.  It seems
pretty durn clear to me that pullup resistors are not needed on the
mode pins at any time, under any circumstances.  The board is due to
come out of layout in a couple of days and I don't want to interrupt
progress.  I don't understand why I can't get a clear answer to this
question.  Peter replied, but didn't answer the question.  I honestly
do not trust the support phone line (because I don't actually talk to
the person who gives the answer, just the gopher who relays the
message) and can't document what I am told verbally.  I can't get an
account to work to get support by email.  So I guess I'll have to
resort to working with the FAE who has already given me bad advice.

For crying out loud, do not make a federal case out of this!

If the documentation asks for a short circuit, then do it!
If your gut feel says there is no need for any external pull-up at all,
then measure the internal pull-up impedance the way I suggested, and if
it is below 3 kilohm, then connect nothing.
If the FAE suggests an external resistor, so use one.
This may be a question of belts or suspenders or both or neither...

But remember: If you want to establish a logical Low level, you must
definitely be cautious and measure whether you are fighting an internal
pull-up.

I much rather spend 10 minutes with a multi-meter than indulge in
contankerous debates in the newsgroup.
We are all engineers and not scribes, aren't we?

Peter Alfke, obviously somewhat irritated...
Like Austin, I am human, too.
Even though we always wear the Xilinx badge, we are still allowed to
voice an opinion...

The documentation DOESN'T say to strap unless you think a schematic in 
an app note is definitive direction on how to treat those pins.

The engineers are bugging rickman because of app notes they saw that 
showed direct connects.

The documentation does not clearly state the condition of the pullups 
for dedicated inputs like the JTAG lines that I couldn't get to work in 
a chain for the life of me a few months ago.

There have been repeated attempts to clarify the datasheet information 
on this board without a clear answer - it's clear that he needs to email 
Steve Knapp directly but that certainly won't help me without follow up 
here.

This is not a federal case and I have been impressed with the civility 
demonstrated by rickman and Austin.

Steve Knapp hasn't appeared to answer the question most explicitly posed 
by Rickman as a clarifying question.

Gut feels do not work when an engineer has to submit to a design review 
process that doesn't allow "gut feel" for a documented follow up to a 
design review action item.

The FAE suggested a resistor which isn't compatible with the Spartan-3 
configuration.

Multimeters work for one part, not for a production design.
____________

I may be asked to consider a Spartan3 as opposed to the 2 big Spartan3Es 
on my one board - if I have to go that route I'll be facing the same 
documentation and the knowledge that there hasn't been a clear answer 
here in these threads.

All that's desired is a straight answer - is that so much to ask?


Peter Alfke wrote:
> For crying out loud, do not make a federal case out of this!
> 
> If the documentation asks for a short circuit, then do it!
> If your gut feel says there is no need for any external pull-up at all,
> then measure the internal pull-up impedance the way I suggested, and if
> it is below 3 kilohm, then connect nothing.
> If the FAE suggests an external resistor, so use one.
> This may be a question of belts or suspenders or both or neither...
> 
> But remember: If you want to establish a logical Low level, you must
> definitely be cautious and measure whether you are fighting an internal
> pull-up.
> 
> I much rather spend 10 minutes with a multi-meter than indulge in
> contankerous debates in the newsgroup.
> We are all engineers and not scribes, aren't we?
> 
> Peter Alfke, obviously somewhat irritated...
> Like Austin, I am human, too.
> Even though we always wear the Xilinx badge, we are still allowed to
> voice an opinion...