In comp.arch (and others) there is a thread on this Opteron Virtex4 coprocessor that sits in socket 940. http://www.dailytech.com/article.aspx?newsid=1920 http://www.theregister.co.uk/2006/04/21/drc_fpga_module/?www.dailytech.com http://www.drccomputer.com/pages/products.html I wonder what others think of this, at $4500 its way to steep for most individual buyers who might happen to have a dual socket Opteron board (I don't), but I wonder if companies like Digilent, Enterpoint and others might see any opportunity to build a much lower cost edu version that is more in line with the cost of an Opteron cpu chip say <$1k and based on best Spartan3 or Virtex2,4 that can still use Webpack. I also wonder how much faster exactly the HT link is over any of the PCI interfaces. John Jakson transputer guy
Opteron HT coprocessors
Started by ●April 28, 2006
Reply by ●April 28, 20062006-04-28
In article <1146246311.256472.241490@j73g2000cwa.googlegroups.com>, "JJ" <johnjakson@gmail.com> writes: |> I wonder what others think of this, at $4500 its way to steep for most |> individual buyers Still way cheaper than a Cray XD-1... Rainer
Reply by ●April 28, 20062006-04-28
Of course that is the point, get rid of what you don't really need, the special purpose motherboards that can only be made in tiny volumes at very high NRE costs, and get on to something alot more HPC people already have, a spare socket perhaps. Next step is to use cheaper parts for entry level but I suppose the PCi... boards could fill that role. John Jakson transputer guy
Reply by ●April 28, 20062006-04-28
JJ (johnjakson@gmail.com) wrote: : In comp.arch (and others) there is a thread on this Opteron Virtex4 : coprocessor that sits in socket 940. : http://www.dailytech.com/article.aspx?newsid=1920 : http://www.theregister.co.uk/2006/04/21/drc_fpga_module/?www.dailytech.com : http://www.drccomputer.com/pages/products.html : I wonder what others think of this, at $4500 its way to steep for most : individual buyers who might happen to have a dual socket Opteron board : (I don't), but I wonder if companies like Digilent, Enterpoint and : others might see any opportunity to build a much lower cost edu version : that is more in line with the cost of an Opteron cpu chip say <$1k and : based on best Spartan3 or Virtex2,4 that can still use Webpack. John, I expect the $4500 reflects development costs and what the market will bear more than anything else - after all the only thing I've seen near it was the old Pilchard FPGA on a DIMM research project. : I also wonder how much faster exactly the HT link is over any of the : PCI interfaces. HT can be implemented much faster than parallel PCI but perhaps more importantly when used with an Opteron is that it's much more tightly coupled to the CPU. Looking at the upcoming HT3 I feel the best is yet to come. One of the posibilities that interest me is a V4 module sitting in a 940 socket with some MGTs wired up (space is tight - I realise that!) - if you happen to be dealing in high speed data aquisition and processing on the bit/word and (large) frame level then a tightly coupled FPGA/commodity CPU system is really quite exciting. cds : John Jakson : transputer guy
Reply by ●April 29, 20062006-04-29
c d saunter wrote:> JJ (johnjakson@gmail.com) wrote: > : In comp.arch (and others) there is a thread on this Opteron Virtex4 > : coprocessor that sits in socket 940. > > : http://www.dailytech.com/article.aspx?newsid=1920 > : http://www.theregister.co.uk/2006/04/21/drc_fpga_module/?www.dailytech.com > : http://www.drccomputer.com/pages/products.html > > : I wonder what others think of this, at $4500 its way to steep for most > : individual buyers who might happen to have a dual socket Opteron board > : (I don't), but I wonder if companies like Digilent, Enterpoint and > : others might see any opportunity to build a much lower cost edu version > : that is more in line with the cost of an Opteron cpu chip say <$1k and > : based on best Spartan3 or Virtex2,4 that can still use Webpack. > > John, > I expect the $4500 reflects development costs and what the market will > bear more than anything else - after all the only thing I've seen near it > was the old Pilchard FPGA on a DIMM research project. >Ofcourse, I recall Xilinx VC funded that or another FPGA-DIMM company, not quite the right time.> : I also wonder how much faster exactly the HT link is over any of the > : PCI interfaces. > > HT can be implemented much faster than parallel PCI but perhaps more > importantly when used with an Opteron is that it's much more tightly > coupled to the CPU. Looking at the upcoming HT3 I feel the best is yet > to come.Much lower latency I hope.> > One of the posibilities that interest me is a V4 module sitting in a 940 > socket with some MGTs wired up (space is tight - I realise that!) - if > you happen to be dealing in high speed data aquisition and processing on > the bit/word and (large) frame level then a tightly coupled > FPGA/commodity CPU system is really quite exciting. >Takes one back to when you could interface 68000s or whatever to your custom logic or even wire wrap your own mobo, its been along time since one could "touch" a processor. Whats you acquisition area?> cds > > : John Jakson > : transputer guy
Reply by ●April 29, 20062006-04-29
JJ (johnjakson@gmail.com) wrote: : > One of the posibilities that interest me is a V4 module sitting in a 940 : > socket with some MGTs wired up (space is tight - I realise that!) - if : > you happen to be dealing in high speed data aquisition and processing on : > the bit/word and (large) frame level then a tightly coupled : > FPGA/commodity CPU system is really quite exciting. : > : Takes one back to when you could interface 68000s or whatever to your : custom logic or even wire wrap your own mobo, its been along time since : one could "touch" a processor. I hate to say it, but that's before my time other than tinkering with the CPU bus sticking out the back of an old Amstrad CPC... There are various things now bringing high end commodity CPUs (as opposed to specialist DSP hardware) and FPGAs close together - offerings from Cray, SGI, this new opteron socketed thingie etc. Most of the fuss is around their use in reconfigurable computing so the offerings tend to be lacking for raw serial IO... : Whats you acquisition area? Starlight - astronomical adaptive optics. Potentially you can be talking about multiple CCDs of many thosands of pixels framing at over 1KHz... cds
Reply by ●May 5, 20062006-05-05
>things now bringing high end commodity CPUs (as opposed to specialist DSP >hardware) and FPGAs close together - offerings from Cray, SGI, this new >opteron socketed thingie etc. Most of the fuss is around their use in >reconfigurable computing so the offerings tend to be lacking for raw >serial IO...>: Whats you acquisition area?>Starlight - astronomical adaptive optics. Potentially you can be talking >about multiple CCDs of many thosands of pixels framing at over 1KHz...CCD -> Hyperthread -> FPGA -> Hyperthread .. other cpu(s). (just a quick thought)
Reply by ●May 6, 20062006-05-06
In article <445bc5dd$0$490$cc7c7865@news.luth.se>, <pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote:>>things now bringing high end commodity CPUs (as opposed to specialist DSP >>hardware) and FPGAs close together - offerings from Cray, SGI, this new >>opteron socketed thingie etc. Most of the fuss is around their use in >>reconfigurable computing so the offerings tend to be lacking for raw >>serial IO... > >>: Whats you acquisition area? > >>Starlight - astronomical adaptive optics. Potentially you can be talking >>about multiple CCDs of many thosands of pixels framing at over 1KHz... > >CCD -> Hyperthread -> FPGA -> Hyperthread .. other cpu(s).I'm not sure that a hypertransport-attached CCD is very practical: HT is a short-range interconnect, and I suspect it's fast enough that you'd have great difficulty implementing it in the rather peculiar fab processes required to make a CCD. I can't find a datasheet for a modern CCD, but the obsolete TC237 has only twelve pins, requires rather complicated digital waveforms on five of them, and outputs analogue pixel data on two more; you want to keep the ADC as close to the detector as possible, I'd have thought connecting the ADCs via an FPGA to gigabit-ethernet channels would be a reasonable way to go, leaving the problem of data acquisition from lots of gigabit ethernet connectors as one already solved by the WAN people. Tom
Reply by ●May 7, 20062006-05-07
Thomas Womack wrote:> In article <445bc5dd$0$490$cc7c7865@news.luth.se>, > <pbdelete@spamnuke.ludd.luthdelete.se.invalid> wrote: > >>things now bringing high end commodity CPUs (as opposed to specialist DSP > >>hardware) and FPGAs close together - offerings from Cray, SGI, this new > >>opteron socketed thingie etc. Most of the fuss is around their use in > >>reconfigurable computing so the offerings tend to be lacking for raw > >>serial IO... > > > >>: Whats you acquisition area? > > > >>Starlight - astronomical adaptive optics. Potentially you can be talking > >>about multiple CCDs of many thosands of pixels framing at over 1KHz... > > > >CCD -> Hyperthread -> FPGA -> Hyperthread .. other cpu(s). > > I'm not sure that a hypertransport-attached CCD is very practical: HT > is a short-range interconnect, and I suspect it's fast enough that > you'd have great difficulty implementing it in the rather peculiar fab > processes required to make a CCD. > > I can't find a datasheet for a modern CCD, but the obsolete TC237 > has only twelve pins, requires rather complicated digital waveforms > on five of them, and outputs analogue pixel data on two more; you > want to keep the ADC as close to the detector as possible, I'd have > thought connecting the ADCs via an FPGA to gigabit-ethernet channels > would be a reasonable way to go, leaving the problem of data > acquisition from lots of gigabit ethernet connectors as one already > solved by the WAN people. > > TomOne fast image sensor project I bumped into that was not an end user camera, was based on a cmos sensor, not that I have ever been impressed with cmos web or picture cameras. In that design I was told of a 4k x 4k sensor with 1KHz or so frame rates with multi stacking of cm size chips, the processing logic was in pixel blocks in a second layer. If the A/D conversion could have been done in pixel tiles parallel style, I am sure one could have put HT on it too (for bottomless $ budget). HT only makes sense in an interactive compute situation, not a input/output only one. The serial data rate would have been quite fast but as you say, better to use standard gig networking that you can use plug n play to any workstation. John Jakson
Reply by ●May 7, 20062006-05-07
Thomas Womack (twomack@chiark.greenend.org.uk) wrote: : I'm not sure that a hypertransport-attached CCD is very practical: HT : is a short-range interconnect, and I suspect it's fast enough that : you'd have great difficulty implementing it in the rather peculiar fab : processes required to make a CCD. : I can't find a datasheet for a modern CCD, but the obsolete TC237 : has only twelve pins, requires rather complicated digital waveforms : on five of them, and outputs analogue pixel data on two more; you : want to keep the ADC as close to the detector as possible, I'd have : thought connecting the ADCs via an FPGA to gigabit-ethernet channels Indeed. Most CCDs are analogue devices with external drivers for a reason - they need rapidly slewing clocks to read them out and very low noise amplifiers + ADCs to digitize the data. For sure gigabit eth or whatever serial protocal may be used, doesn't rally matter as long as the rate's high enough and the latency low enough - it'd just be nice if the opteron socketed FPGA and similar projets had serial transcievers to talk such high speed serial links :-) cds
