ISE 8.1 Comment Bug, Very hideous

The following code was shown to me by a collegue.  All of the logic has 
been removed for clarity (and to protect IP).  The Synthsizer reports 3 
errors that some of the signals are not declared as input, inout or 
output.    If you remove the line comments in front of the input and 
output declarations, the program synthsizes as expected.


8.1  YUCK!!



-Eli

Eli Hughes wrote:
> The following code was shown to me by a collegue.  All of the logic has 
> been removed for clarity (and to protect IP).  The Synthsizer reports 3 
> errors that some of the signals are not declared as input, inout or 
> output.    If you remove the line comments in front of the input and 
> output declarations, the program synthsizes as expected.
> 
> 
> 8.1  YUCK!!
> 
> 
> 
> -Eli


Oops, here is the verilog code:

module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 , 
COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo);

	

/*inputs outputs registers wires*/
	input					SysReset;
	output				Zero;
	input					ClkInput;
	input					UZBEERX;
	output	[12:0]	ROW_Q1;	// row select quadrant1
	output	[12:0]	COL_Q1;	// column select quadrant1
	output	[12:0]	ROW_Q2;	// row select quadrant2
	output	[12:0]	COL_Q2;	// column select quadrant2
	output	[12:0]	ROW_Q3;	// row select quadrant3
	output	[12:0]	COL_Q3;	// column select quadrant3
	output	[12:0]	ROW_Q4;	// row select quadrant4
	output	[12:0]	COL_Q4;	// column select quadrant4
	output	[3:0]		PSUP;
	output	[3:0]		PSUPo;
	
	
endmodule

some long time ago writing your company name in non-ascii chars like
a-umlaut a" in the schematic template header of the Xilinx ECS rendered
the schematic to invalid, so you lost your work (ok it was possible to
use binary editor to fix the char)

- the comment type of error in Xilinx ISE/XST means that Xilinx is not
using a proper qualified VHDL/verilog parser - a proper parser would
not chokes on comments (in places where those are legal as per language
reference)

Antti

Eli-

> If you remove the line comments in front of the input and
> output declarations, the program synthsizes as expected

This happens in 7.1 also.  A couple of years ago a Xilinx FAE told us
"do not use C++ style comments for any reason except synthesis
attributes" and we have followed that on blind faith.

-Jeff

Jeff Brower wrote:
> Eli-
> 
> 
>>If you remove the line comments in front of the input and
>>output declarations, the program synthsizes as expected
> 
> 
> This happens in 7.1 also.  A couple of years ago a Xilinx FAE told us
> "do not use C++ style comments for any reason except synthesis
> attributes" and we have followed that on blind faith.
> 
> -Jeff
> 


So, if I cant use //  or /* */, what can I use for commenting?

-Eli

Eli Hughes wrote:

> Eli Hughes wrote:
> 
>> The following code was shown to me by a collegue.  All of the logic 
>> has been removed for clarity (and to protect IP).  The Synthsizer 
>> reports 3 errors that some of the signals are not declared as input, 
>> inout or output.    If you remove the line comments in front of the 
>> input and output declarations, the program synthsizes as expected.

Wow, that's a pretty impressive impact/laziness ratio ::

(User Impact x N users) / (Suppliers Time to Fix)

How long _should_ it take to fix this ?

-jg


>>
>>
>> 8.1  YUCK!!
>>
>>
>>
>> -Eli
> 
> 
> 
> Oops, here is the verilog code:
> 
> module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 , 
> COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo);
> 
>     
> 
> /*inputs outputs registers wires*/
>     input                    SysReset;
>     output                Zero;
>     input                    ClkInput;
>     input                    UZBEERX;
>     output    [12:0]    ROW_Q1;    // row select quadrant1
>     output    [12:0]    COL_Q1;    // column select quadrant1
>     output    [12:0]    ROW_Q2;    // row select quadrant2
>     output    [12:0]    COL_Q2;    // column select quadrant2
>     output    [12:0]    ROW_Q3;    // row select quadrant3
>     output    [12:0]    COL_Q3;    // column select quadrant3
>     output    [12:0]    ROW_Q4;    // row select quadrant4
>     output    [12:0]    COL_Q4;    // column select quadrant4
>     output    [3:0]        PSUP;
>     output    [3:0]        PSUPo;
>     
>     
> endmodule

FWIW the following code seems to work with ise 8.1.03:

module test (test_in1, test_in2, test_out1, test_out2);

input test_in1; // comment here
input test_in2; /* comment here */

output /* comment here */ test_out1;
output test_out2; /* comment
                   here
                   and
                   here
                   */

assign test_out1 = test_in1;
assign test_out2 = test_in2;

endmodule // test

HTH,
Jim
http://home.comcast.net/~jimwu88/tools

Eli Hughes wrote:
> Eli Hughes wrote:
> > The following code was shown to me by a collegue.  All of the logic has
> > been removed for clarity (and to protect IP).  The Synthsizer reports 3
> > errors that some of the signals are not declared as input, inout or
> > output.    If you remove the line comments in front of the input and
> > output declarations, the program synthsizes as expected.
> >
> > 8.1  YUCK!!
> >
> > -Eli
>
>
> Oops, here is the verilog code:
>
> module Main(SysReset,Zero,ClkInput, UZBEERX, ROW_Q1, COL_Q1, ROW_Q2 ,
> COL_Q2 , ROW_Q3 , COL_Q3 , ROW_Q4,COL_Q4,PSUP,PSUPo);
>
> /*inputs outputs registers wires*/
> 	input					SysReset;
> 	output				Zero;
> 	input					ClkInput;
> 	input					UZBEERX;
> 	output	[12:0]	ROW_Q1;	// row select quadrant1
> 	output	[12:0]	COL_Q1;	// column select quadrant1
> 	output	[12:0]	ROW_Q2;	// row select quadrant2
> 	output	[12:0]	COL_Q2;	// column select quadrant2
> 	output	[12:0]	ROW_Q3;	// row select quadrant3
> 	output	[12:0]	COL_Q3;	// column select quadrant3
> 	output	[12:0]	ROW_Q4;	// row select quadrant4
> 	output	[12:0]	COL_Q4;	// column select quadrant4
> 	output	[3:0]		PSUP;
> 	output	[3:0]		PSUPo;
>
> endmodule

Quick question: why aren't you using the modern ANSI-C-style
declarations?

-a

Eli-

> So, if I cant use //  or /* */, what can I use for commenting?

By "line comments" I thought you meant C++ style comments.  I've not
had trouble with /* ... */ in 7.1, only with //.  My apologies for
answer that was not helpful.

-Jeff

Jeff Brower wrote:
> Eli-
>
> > So, if I cant use //  or /* */, what can I use for commenting?
>
> By "line comments" I thought you meant C++ style comments.  I've not
> had trouble with /* ... */ in 7.1, only with //.  My apologies for
> answer that was not helpful.
>
> -Jeff

I am the collegue Eli spoke of. I did not have problems with 7.1, only
8.1. I have also noticed that pushing the enter button does not go to
the next line until I start typing after pressing enter. Also, after a
// comment, if I press enter, the next line actually turns green. I had
to delete and press enter a few times to get it to not show up green
like a comment, but the synthesiser still recognizes it as one, as seen
in Eli's example.

-Jon