Forcing Synopsys to use only DFFs

I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush radiation induced errors with TMR corrected values.

The FPGA that I am using can implement enable FFs or D FFs.  Is it possible to force Synopsys to not use only D FFs to assure that the stored values are updated on every clock?

-Chris

On Thursday, October 20, 2022 at 12:50:02 PM UTC-4, emai...@gmail.com wrote:
> I have an application that needs to assure that the FFs reloaded from the combinatorial logic at their inputs on every clock in order to flush radiation induced errors with TMR corrected values. 
> 
> The FPGA that I am using can implement enable FFs or D FFs. Is it possible to force Synopsys to not use only D FFs to assure that the stored values are updated on every clock? 

You can assure enables are not used by specifying the logic to be used on every possible combination of inputs, and not using any conditionals with unlisted conditions.  For example: 

if (rising_edge(clk)) then
  if (A = B) then 
    D <= C or E;
  else
    D <= C and E;
  end if; 
end if;

This will use a DFF only because every condition is specified and the FF does not need to remember its state. 

if (rising_edge(clk)) then
  if (A = B) then 
    D <= D or C;
  end if; 
end if;

This will generate an enable because there is no ELSE clause.   Same for CASE statements, etc.  Every possible condition must have a value specified for the D input. 

Likewise, this will use an enable.  

if (rising_edge(clk)) then
  if (A = B) then 
    D <= C or E;
  else
    D <= D;
  end if; 
end if;

No condition should simply feedback the output to the D input.  This will also generate an enable input, since in the ELSE clause the FF does not need a D input, it only needs to remember its previous value. 

I had never given this much thought before, but it's possible that to be certain there are no enables generated, that  you can't have any combinational path from the FF output to the D input at all.  So this might also need to be excluded. 

if (rising_edge(clk)) then
  if (A = B) then 
    D <= C or E;
  else
    D <= C or D;
  end if; 
end if;

I would need to give some thought to possible conditions that might make use of an enable in this case. 

-- 

Rick C.

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