Chaining multiple Xilinx "Six Easy Pieces" Clock Doubler

Hi group,

Are there any problems with chaining multiple instances of the clock
doubler from this link together?

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=pa_six_easy
(http://tinyurl.com/aqk9f)  (see section 6)

Clock rate variations preclude the use of DCMs (even in low frequency
mode using CLKFX only).

Many thanks for your time.

Dave a �crit :
> Hi group,
> 
> Are there any problems with chaining multiple instances of the clock
> doubler from this link together?
[...]
> Clock rate variations preclude the use of DCMs (even in low frequency
> mode using CLKFX only).


Hello
Look at the output waveform: this circuit generates a *pulse* on each 
transition of the input signal. If you chain a second circuit, it will 
generate pairs of pulses (about 2ns apart, from the circuit description) 
on each transition of the input signal, and so on. Your average output 
frequency will actually be 2**n (n being the number of pseudo-doublers 
in your chain) but your duty cycle will be almost random. Read "unusable"

Nicolas

NO !! Do not cascade that frequency double circuit.
As a single instant, the circuit is (or can be made to be) safe and
reliable, but a cascade would generate garbage.
Peter Alfke

OK.  Many thanks for the quick answers.  I knew it couldn't be so
easy...

Dave-

> Clock rate variations preclude the use of DCMs (even in low frequency
> mode using CLKFX only).

With freq variations or even complete clock stop, you can still use
DCMs, and use an sm based on an independent, reliable clock to measure
the actual DCM output (not the LOCKED signal, which I found to be
unreliable).  If it locks up or starts producing bogus duty cycle, then
follow the procedures for Reset.

I've had good luck with this approach.

-Jeff

Dave wrote:
> Hi group,
> 
> Are there any problems with chaining multiple instances of the clock
> doubler from this link together?
> 
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=&iLanguageID=1&multPartNum=1&sTechX_ID=pa_six_easy
> (http://tinyurl.com/aqk9f)  (see section 6)
> 
> Clock rate variations preclude the use of DCMs (even in low frequency
> mode using CLKFX only).
> 
> Many thanks for your time.

What are you trying to do ?

Chain of a simple clock doubler is not practical, but there
are other solutions.

eg If you need 8 clocks to spin a state engine, for each incomming edge, 
than that can be done. Create a Gated Ring Osc, counter and XOR CE, and 
clock the counter until chosen /N bit equals Fin.
  This gives a burst of edges, syncronised with the input signal, but
they are not evenly spaced, or phase-located;
  You get (eg) 8 clocks for each input edge.

-jg

Hi Jeff,

Sounds interesting.  Unfortunately, the input clock will sometimes be
lower than 1MHz and the output must be > 24MHz so a DCM cannot be used
at all.

I see there is a reset pin on the DCM.  I assume the procedures for
reset are to stop using the output clock when it is messed up, assert
reset and wait for a good clock again before using teh output once
more?

Many thanks,

Dave

Hi Jim,

What is required is to generate 2x, 4x and 8x clocks from the input.
Could be done using 3 DCMs (assuming in range inputs/outputs) each
doing 2x.

The appropriate clock would then be selected and used.

Your method of generating 8 edges sounds cool but I think a regular
clock will be required rather than a bursty one.

Cheers,

Dave

Dave wrote:
> Hi Jim,
> 
> What is required is to generate 2x, 4x and 8x clocks from the input.
> Could be done using 3 DCMs (assuming in range inputs/outputs) each
> doing 2x.
> 
> The appropriate clock would then be selected and used.
> 
> Your method of generating 8 edges sounds cool but I think a regular
> clock will be required rather than a bursty one.

  You have not defined what 'clock rate variations' will be.
  A regular locked multiple is only possible with a regular
referance IP. Wobble the IPs and the DCMs will chase their tail
trying to follow....
  So, you will need to nail down the dF and Slews (dF/dT) and also when 
it does, and does not, have to follow with 8x outputs - and then try
some designs.
-jg

>   You have not defined what 'clock rate variations' will be.
>   A regular locked multiple is only possible with a regular
> referance IP. Wobble the IPs and the DCMs will chase their tail
> trying to follow....
>   So, you will need to nail down the dF and Slews (dF/dT) and also when
> it does, and does not, have to follow with 8x outputs - and then try
> some designs.

Hi Jim,

The input clock may be as low as 200 kHz and as high as 20-30MHz
perhaps.  The frequency will be fixed at a certain frequency while the
system runs however (i.e. it is not going to swing around in that
range!).

The issue is that 2x, 4x and 8x are required.  The minimum output of
the DCM when using CLKFX is 24MHz so 12MHz is the minimum input but
downto 200kHz as input is required.  Also, 1MHz is min input of DCM and
lower freqs than this may be used.  So, DCMs cannot be used.

Many thanks for your help,

Dave