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ports of multidimentional arrays in verilog.

Started by CMOS May 3, 2006
hi,

using verilog how to write a module which has an inpput port for an
array of 8 bit signals and how to write a test bench for it.

thank you.
CMOS

Write it as several 8-bit vectors or as one n*8 bit vector.  You can't pass 
arrays in Verilog or Verilog2001.
There's also comp.lang.verilog.

"CMOS" <manusha@millenniumit.com> wrote in message 
news:1146677836.868136.228860@g10g2000cwb.googlegroups.com...
> hi, > > using verilog how to write a module which has an inpput port for an > array of 8 bit signals and how to write a test bench for it. > > thank you. > CMOS >
CMOS-

> using verilog how to write a module which has an inpput port for an > array of 8 bit signals and how to write a test bench for it.
Wait until you try to initialize your arrays. Try this search in Google Groups: initializing array of registers in XST group:comp.arch.fpga It has been suggested that RAMs in general work better and are more flexible than arrays or registers or wires. I'm not sure though on whether it's possible to pass a RAM or RAM "base address" to a module. -Jeff