Xilinx 3s8000?

Mike Harrison wrote:
> Presumably you could do it rather quicker using the S3's multiplier blocks.....

Good point, but then I'd be tied into a particular FPGA. The multipliers 
are very impressive however. If I ever get my design to fit on 
something, then I can start taking advantage of things like the built-in 
multipliers to speed things up. Lets see, 18x18->36 bits in less than 5 
ns. For a 1024 bit multiply, it would take roughly 1,624 eighteen bit 
multiplies and a bunch of multi-precision additions, which translates 
into around 8 microseconds per 1024 bit word! Very impressive indeed.

Ron

P.S.
Before someone catches my error, yes indeed you could run some of these 
multiplies in parallel to cut the timing even more. The datasheet says 
the Spartan-3E devices have between 4 to 36 dedicated multiplier blocks 
per device, so depending on how many there are on the FPGA the 8 
microseconds I mentioned earlier could be cut by as much as 1/4 to 
1/36th to 22ns for 1024 bits!!! I will definitely have to look into this 
at some point. It would be great if a multiprecision package for the 
multipliers were already available in Verilog.

Eight microseconds divided by 36 equals 222 nanoseconds.
No obscenities please.
Peter Alfke
==================================
Ron wrote:
> P.S.
> Before someone catches my error, yes indeed you could run some of these
> multiplies in parallel to cut the timing even more. The datasheet says
> the Spartan-3E devices have between 4 to 36 dedicated multiplier blocks
> per device, so depending on how many there are on the FPGA the 8
> microseconds I mentioned earlier could be cut by as much as 1/4 to
> 1/36th to 22ns for 1024 bits!!! I will definitely have to look into this
> at some point. It would be great if a multiprecision package for the
> multipliers were already available in Verilog.

Peter Alfke wrote:
> Eight microseconds divided by 36 equals 222 nanoseconds.

Keyboard bounce. ;-)

Since this discussion is veering back and forth between being on-topic,
I suppose I can throw my two cents in.

I am both a professional and hobby FPGA developer. At work, I get all
kinds of fancy Virtex and Stratix parts to target. At home, I have a
Cyclone II 2C35 (on an Altera DE2 board) and the Xilinx sample pack I
got for free. Both use free tools from Altera and Xilinx respectively.

First, the silicon is interesting, but not terribly hard anymore. The
basic features are common to all manufacturers. The real magic is in
the mapping and PAR. Why else would someone pay for Synplicity
software? Thus, the software tools that Ron disparages are probably
worth the money considering what they do. I recognize that, and accept
that it costs money to keep the tools up to date.

That said, I wish vendors didn't feel the need to disown older parts
when it isn't difficult to keep support as an option. I can still
output from Microsoft Word to all kinds of strange, esoteric (and
ancient) formats. Why can't Xilinx allow me to use the latest ISE to
target strange, esoteric FPGA's? Simply make it an optional component.
At the very least, let me download a support module from your website -
if putting it on the DVD is too much trouble.

As it stands, at work I have to keep a copy of ISE 4.2i, because it is
the last version that supports the XC4000E series FPGA's - and it
doesn't play well when install alongside 7.1i - which means a dedicated
terminal just for 4.2i. This is BLOODY FRUSTRATING. I realize the parts
are old, but they are still out there - and designs do occasionally
need maintenance. BTW - Austin was bragging about a lot of military and
space applications. Guys, we actually support those designs for more
than 5 years. It would be helpful if your tools did as well.

As for the cost issue, the webpacks cover all but the high-end parts. I
have found them perfectly adequate for home use. I'm actually impressed
that Xilinx or Altera offer free versions at all. Seriously, you get a
VHDL/Verilog compiler, limited simulation, mapping and PAR - for free?
That's almost absurd. The only tool I don't have at  home is Synplify
Pro - I end up using Quartus and XST.

As a fairy tale wish, it would be nice if there was an academic pricing
plan that could include guys like me that want to develop at home,
without having to run to the office to compile something. Yes, it is a
different market - but with just a little forethought, you could offer
great pricing to students and hobbyists, while retaining the high-end
corporate accounts. I would gladly pay several hundred for a
_perpetual_ license that had restrictions on what commercial activities
were allowed, yet let me play with the larger parts on boards from
Digilent, BurchEd, etc. (I would even be OK with the software being
tied TO the boards - maybe lock on the FPGA serial number via JTAG or
something)

Much like the GPL, if you want to do something outside the license,
like start a business, you cough up for an unrestricted license. Yes,
there would be a trust element, but since you are also the
manufacturer, it wouldn't be difficult to see a spike in part orders.

Something to think about - since I know I would like to play with the
Virtex parts with embedded PPC cores - but can't afford to ante-up to
the full package.

In article <G9R7g.135$7q7.106@fe05.lga>, News5@spamex.com 
says...
> Mike Harrison wrote:
> > Presumably you could do it rather quicker using the S3's multiplier blocks.....
> 
> Good point, but then I'd be tied into a particular FPGA. The multipliers 
> are very impressive however. If I ever get my design to fit on 
> something, then I can start taking advantage of things like the built-in 
> multipliers to speed things up. Lets see, 18x18->36 bits in less than 5 
> ns. For a 1024 bit multiply, it would take roughly 1,624 eighteen bit 
> multiplies and a bunch of multi-precision additions, which translates 
> into around 8 microseconds per 1024 bit word! Very impressive indeed.

The multipliers are built in dedicated logic, so using 
them will allow you to fit a larger block into a given 
device. IOW, using them will contribute directly to 
making your design fit.

-- 
    Later,
    Jerry.

The universe is a figment of its own imagination.

radarman wrote:
<snip>
> That said, I wish vendors didn't feel the need to disown older parts
> when it isn't difficult to keep support as an option. I can still
> output from Microsoft Word to all kinds of strange, esoteric (and
> ancient) formats. 

That's partly because of lawsuits, when Microsoft has attempted to
EOL products lines, which has meant excluding still-working-fine PCs.

> Why can't Xilinx allow me to use the latest ISE to
> target strange, esoteric FPGA's? Simply make it an optional component.
> At the very least, let me download a support module from your website -
> if putting it on the DVD is too much trouble.
> 
> As it stands, at work I have to keep a copy of ISE 4.2i, because it is
> the last version that supports the XC4000E series FPGA's - and it
> doesn't play well when install alongside 7.1i - which means a dedicated
> terminal just for 4.2i. This is BLOODY FRUSTRATING. I realize the parts
> are old, but they are still out there - and designs do occasionally
> need maintenance. BTW - Austin was bragging about a lot of military and
> space applications. Guys, we actually support those designs for more
> than 5 years. It would be helpful if your tools did as well.

The short design life of tools has to be impacting their silicon sales, 
and as you point out, engineering support requires working tools.

-jg

Jerry Coffin wrote:
> The multipliers are built in dedicated logic, so using 
> them will allow you to fit a larger block into a given 
> device. IOW, using them will contribute directly to 
> making your design fit.

I was wondering about that. There would be a great deal of routing, 
shifting, etc., in a design that does multi-precision multiplication 
however, and as slow as the design I'm using now is, it's about as 
minimal as it's possible to get I think (basically a couple of shift 
registers, with test and conditional add).

I think I'll go search around and see if I can find some sort of 
multi-precision multiplication module(s) in Verilog on the net somewhere 
just to get started quickly. If anyone happens to know of anything like 
that, please post a link.

Thanks,

Ron

Ron wrote:

> Jerry Coffin wrote:
> 
>> The multipliers are built in dedicated logic, so using them will allow 
>> you to fit a larger block into a given device. IOW, using them will 
>> contribute directly to making your design fit.
> 
> 
> I was wondering about that. There would be a great deal of routing, 
> shifting, etc., in a design that does multi-precision multiplication 
> however, and as slow as the design I'm using now is, it's about as 
> minimal as it's possible to get I think (basically a couple of shift 
> registers, with test and conditional add).
> 
> I think I'll go search around and see if I can find some sort of 
> multi-precision multiplication module(s) in Verilog on the net somewhere 
> just to get started quickly. If anyone happens to know of anything like 
> that, please post a link.

  Also look at the newest Lattice devices, they have DSP blocks, with
more in them.
  If you can wear your 'humble and polite researcher' hat, you might be
able to get a loan of the full tool chain :)
  It would be in their interests to have the flow tested on wide data paths.

-jg

Radarman, I agre with most of what you wrote, but I am not the boss
here...
One exception, though:
" Why can't Xilinx allow me to use the latest ISE to
target strange, esoteric FPGA's? Simply make it an optional component."
Making the newest software compatible with XC3000 nd XC4000 would be a
nightmare for our developers. They might declare it so difficult as to
be virtually impossible. Backwards compatibility is a nightmare for any
software developer (my son works at Apple R&D...)
Otherwise you have some good ideas.
It's just that our software developer have their plate full with urgent
and vital projects, so that the things you mention often don't rise
high enough.
BTW, at work, I get some anusing comments about the insults I have to
endure here. But they are so outlandish that they do not really hurt...
Peter Alfke
Peter Alfke