Funky experiment on a Spartan II FPGA

Hi all,

I am trying to do a novel kind of experiment using a spartan II FPGA. I
want to measure the impedence profile (spectrum) of the Vdd and ground
planes on the FPGA. To do that, I am planning to do the following
(a) fill up the FPGA with a lot of synchronous logic
(b) clock it at different frequencies
(c) measure the voltage and current consumed at every frequency.

To make the measurements independent of the program running on the
FPGA, I am planning to hold all the logic on the FPGA in the reset
state.

Right now, I am planning to implement a few Picoblaze cores on my 50k
gate spartan II . (each picoblaze roughly takes up 9% of the slices),
tie them up and implement some test logic on the FPGA.

I am basically using the forum as a sounding board for my idea. Any
suggestions on what cores I should implement for maximum sensitivity ?
Is picoblaze a good idea ?

Thanks
Mammo

For a worst-case look, I would implementa maximum-lemgth shift register
and toggle its front end. Driven by a global clock,this generates the
maximum amplitude of synchronous spikes on the Vcc distribution.
Anything more realistic would spread out the spikes, thus lowering the
amplitude.
I suppose you know how to access the internal Vcc and Vdd levels, and
bring them to the outside.
My question is: What do you want to prove or disprove?
Peter Alfke, from home.

mammo wrote:
> Hi all,
> 
> I am trying to do a novel kind of experiment using a spartan II FPGA. I
> want to measure the impedence profile (spectrum) of the Vdd and ground
> planes on the FPGA. To do that, I am planning to do the following
> (a) fill up the FPGA with a lot of synchronous logic
> (b) clock it at different frequencies
> (c) measure the voltage and current consumed at every frequency.
> 
> To make the measurements independent of the program running on the
> FPGA, I am planning to hold all the logic on the FPGA in the reset
> state.

this bit has me lost, how can you use a picoblaze in the reset state ?

> Right now, I am planning to implement a few Picoblaze cores on my 50k
> gate spartan II . (each picoblaze roughly takes up 9% of the slices),
> tie them up and implement some test logic on the FPGA.
> 
> I am basically using the forum as a sounding board for my idea. Any
> suggestions on what cores I should implement for maximum sensitivity ?
> Is picoblaze a good idea ?

yes, it is widely known, and is a more typical usage of PFGA,

You could also implement a 'sea of 32 bit CE counters', which can be 
usefull to calibrate and verify your system - that is a pattern that
should not overheat the FPGA, but will give a stable spectrum.
Enable/disable of the ClockEnable, would also give results for the
clock tree and (plus) the logic fabric.

-jg

Peter,
>My question is: What do you want to prove or disprove?

Thanks for your suggestion. This is essentially a curiosity driven
experiment. We saw a paper in the Intel Technology journal , where they
had such impledence measurements for the P4 processor. We were
wondering if we could reproduce those measurements in our lab, and
decided to start with FPGAs rather than processors as a first baby
step.
The paper is located at:
http://www.intel.com/technology/itj/2005/volume09issue04/art02_powerdelivery/p01_abstract.htm

Also, just checking if I understand you right : are you suggesting that
I implement one huge shift register, and then just push a 10101...
pattern through it ? it seems like a good idea.

Jim,
>> To make the measurements independent of the program running on the
>> FPGA, I am planning to hold all the logic on the FPGA in the reset
>> state.
>
>this bit has me lost, how can you use a picoblaze in the reset state ?

Since I donot really want to do any real computations using the
Picoblaze, i think its okay to hold it in the reset state. I just want
to clock it at different frequencies and see what happens on the power
delivery network

Thanks for your suggestion about the clock enable. It makes a lot of
sense.

Regards,
mammo

mammo wrote:
> Jim,
> 
>>>To make the measurements independent of the program running on the
>>>FPGA, I am planning to hold all the logic on the FPGA in the reset
>>>state.
>>
>>this bit has me lost, how can you use a picoblaze in the reset state ?
> 
> 
> Since I donot really want to do any real computations using the
> Picoblaze, i think its okay to hold it in the reset state. I just want
> to clock it at different frequencies and see what happens on the power
> delivery network
> 
> Thanks for your suggestion about the clock enable. It makes a lot of
> sense.

There are two portions of clock consumption, one is the clock network
itself, and the other is the Nodes/Fabric that toggle.
Not all data makes that distinction.

So Peter's more agressive test of a 101010 shift register will have
two power levels, depending on the ClockEnable.
Wide counters have a more typical logic % usage.

If you Pinmap, and add an OE term, you can also get the IO fabric power 
values.

The separate supplies on FPGA makes probe of the internal power rails
more difficult.

-jg

Correction, before anybody points out my error:
The long checkerboard shift register is a popular way to measure power
consumption, but it is actually very benign with respect to Vcc spikes,
since half the loads go Low and half go High, nicely compensting each
other.
The tougher test is to switch every bit in synchronism, from Low to
High on one clock, and from High to Low on the next, etc.
Needs a line to drive all D inputs together, and this line being
toggled.
This is of course not a realistic test, and it may show real ugly
results.
But I think that's what you were after...
Sorry for the misleading previous posting.
Peter Alfke, Xilinx (from home)

mammo wrote:
> Hi all,
>
> I am trying to do a novel kind of experiment using a spartan II FPGA. I
> want to measure the impedence profile (spectrum) of the Vdd and ground
> planes on the FPGA. To do that, I am planning to do the following
> (a) fill up the FPGA with a lot of synchronous logic
> (b) clock it at different frequencies
> (c) measure the voltage and current consumed at every frequency.
>
> To make the measurements independent of the program running on the
> FPGA, I am planning to hold all the logic on the FPGA in the reset
> state.
>
> Right now, I am planning to implement a few Picoblaze cores on my 50k
> gate spartan II . (each picoblaze roughly takes up 9% of the slices),
> tie them up and implement some test logic on the FPGA.
>
> I am basically using the forum as a sounding board for my idea. Any
> suggestions on what cores I should implement for maximum sensitivity ?
> Is picoblaze a good idea ?
> 
> Thanks
> Mammo

Hi Mammo,

I think this would be a great project, and a useful paper to present
for others too.

I'm not sure why Peter is talking about worst case, as Xilinx has
already said the larger parts lack margin to operate at the highest
frequencies with worst case design loads due to power and thermal
issues.  Besides the lack of cooling for worst case loads, most boards
also lack the power supply margins too ... and will go unstable at
worst case loading at high clock rates due to dynamic power.

It would be nice (and I've asked for this before with very negative
responses) that Xilinx openly document the dynamic power and thermal
limits. As a side note, this problem is partially mitigated by clock
skew as the parts get larger, but that doesn't help realize designing
for worst case loading, or even having a clue to predict why one
placement works and another fails, when the skew stacks up worst case
in your design.

Have fun!! ... and I look forward to your results :)

John


mammo wrote:
> Hi all,
>
> I am trying to do a novel kind of experiment using a spartan II FPGA. I
> want to measure the impedence profile (spectrum) of the Vdd and ground
> planes on the FPGA. To do that, I am planning to do the following
> (a) fill up the FPGA with a lot of synchronous logic
> (b) clock it at different frequencies
> (c) measure the voltage and current consumed at every frequency.
>
> To make the measurements independent of the program running on the
> FPGA, I am planning to hold all the logic on the FPGA in the reset
> state.
>
> Right now, I am planning to implement a few Picoblaze cores on my 50k
> gate spartan II . (each picoblaze roughly takes up 9% of the slices),
> tie them up and implement some test logic on the FPGA.
>
> I am basically using the forum as a sounding board for my idea. Any
> suggestions on what cores I should implement for maximum sensitivity ?
> Is picoblaze a good idea ?
> 
> Thanks
> Mammo

Peter Alfke wrote:
> Correction, before anybody points out my error:
> The long checkerboard shift register is a popular way to measure power
> consumption, but it is actually very benign with respect to Vcc spikes,
> since half the loads go Low and half go High, nicely compensting each
> other.
> The tougher test is to switch every bit in synchronism, from Low to
> High on one clock, and from High to Low on the next, etc.
> Needs a line to drive all D inputs together, and this line being
> toggled.
> This is of course not a realistic test, and it may show real ugly
> results.
> But I think that's what you were after...
> Sorry for the misleading previous posting.
> Peter Alfke, Xilinx (from home)

To implement both would be a good idea.
That way, you have two tests with similar node-toggle rates, but
different Icc profiles.
Another would be to configure (tiled) half the device as PosEdge and 
half as NegEdge, as that shifts the fabric currents. (but not the 
Clock-tree currents ).
-jg

Hey people,

Thanks for all the suggestions... will keep you guys posted.

Best,
mammo