How to check IOB register packing?

Hi,
I am using the "syn_useioff = 1" directive in my top module to pack the
Input/Output registers into the IOB and synthesizing using Synplify
Pro. For PAR, I am using Xilinx ISE 7.1
I would like to know how to check and see whether the input and output
registers are packed in the IO blocks after PAR.
Also, I am tri-stating my outputs based on a control signal by using
the following syntax in verilog : out_data = 16'bz. So, I want to check
whether the tri-state buffers and the output registers are placed in
the same IOB. Can this be done? Some people are telling that this
verilog syntax will not actually tri-state the outputs in
implelementation and I have to specifically instantiate the tri-state
buffers from Xilinx. Can anyone clarify me about this?

Thanks & Regards,
Srini.

srini wrote:
> I would like to know how to check and see whether the input and output
> registers are packed in the IO blocks after PAR.

Look in xilinx's map report file (*.mrp). Near the end there is a table 
with a row for each IO signal and its characteristics including what IOB 
registers are used (OFF - output flipflop, IFF - input flipflop, ODDR - 
output double datarate, IDDR - input double datarate, ENFF - tristate 
enable flipflop,....)

> Also, I am tri-stating my outputs based on a control signal by using
> the following syntax in verilog : out_data = 16'bz. So, I want to check
> whether the tri-state buffers and the output registers are placed in
> the same IOB. Can this be done? Some people are telling that this
> verilog syntax will not actually tri-state the outputs in
> implelementation and I have to specifically instantiate the tri-state
> buffers from Xilinx. Can anyone clarify me about this?
Here's an example of inferring tri-state IOs:
    assign   EthMiiDat    = EthMiiDatT ? 1'bZ: EthMiiDatO;
    assign   EthMiiDatI   = EthMiiDat;

The IO Pin is EthMiiDat. Three signals go to the FPGA fabric: EthMiiDatO 
is the output, EthMiiDatI is the input and EthMiiDatT is the tri-state 
enable.

---
Joe Samson
Pixel Velocity

Another way to verify this is to open the ncd file in FPGA_EDITOR and
see what are put in the IOBs.

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/

Jim Wu wrote:

> Another way to verify this is to open the ncd file in FPGA_EDITOR and
> see what are put in the IOBs.
> 
> HTH,
> Jim
> http://home.comcast.net/~jimwu88/tools/
> 
Or look at the pad report, there is a column there indicating whether 
the signal is registered or not for each pad.

Hi,
In the map report file, all the input and output signals are listed
under the IOB name column in the IOB properties section. But under the
reg(s) column, only my clock outputs have the OFF1 entry and all other
input and ouput signals have no entry of IFF/OFF/ENFF. What does it
mean?

"srini" <g.shrinivasan@gmail.com> wrote in message 
news:1147421219.221889.122660@g10g2000cwb.googlegroups.com...
> Hi,
> I am using the "syn_useioff = 1" directive in my top module to pack the
> Input/Output registers into the IOB and synthesizing using Synplify
> Pro. For PAR, I am using Xilinx ISE 7.1
> I would like to know how to check and see whether the input and output
> registers are packed in the IO blocks after PAR.
> Also, I am tri-stating my outputs based on a control signal by using
> the following syntax in verilog : out_data = 16'bz. So, I want to check
> whether the tri-state buffers and the output registers are placed in
> the same IOB. Can this be done? Some people are telling that this
> verilog syntax will not actually tri-state the outputs in
> implelementation and I have to specifically instantiate the tri-state
> buffers from Xilinx. Can anyone clarify me about this?
>
> Thanks & Regards,
> Srini.

Me, I like to have an OFFSET OUT AFTER constraint that gives a Tco value 
slightly larger than the guaranteed clock-to-out time for my I/O standards. 
If I don't have a register packed in the IOB, there's a failure in the 
timing constraint. 

srini wrote:
> Hi,
> In the map report file, all the input and output signals are listed
> under the IOB name column in the IOB properties section. But under the
> reg(s) column, only my clock outputs have the OFF1 entry and all other
> input and ouput signals have no entry of IFF/OFF/ENFF. What does it
> mean?
> 
It means that those IOs aren't registered in the IOB. If you want to 
figure out why, I suggest you search comp.arch.fpga.

http://groups.google.com/group/comp.arch.fpga/search?group=comp.arch.fpga&q=iob+register&qt_g=1&searchnow=Search+this+group


---
Joe Samson
Pixel Velocity

"John_H" <johnhandwork@mail.com> wrote in message 
news:8N19g.698$oa1.536@news02.roc.ny...
>
> Me, I like to have an OFFSET OUT AFTER constraint that gives a Tco value 
> slightly larger than the guaranteed clock-to-out time for my I/O 
> standards. If I don't have a register packed in the IOB, there's a failure 
> in the timing constraint.
Neat! 

Ray Andraka <ray@andraka.com> wrote:

>Jim Wu wrote:
>
>> Another way to verify this is to open the ncd file in FPGA_EDITOR and
>> see what are put in the IOBs.
>> 
>> HTH,
>> Jim
>> http://home.comcast.net/~jimwu88/tools/
>> 
>Or look at the pad report, there is a column there indicating whether 
>the signal is registered or not for each pad.

Or set static timing constratints on all pins that can only be reached
with IOB FFs...


--
Phil Hays

Hi Phil,
I am new to using these tools and designing with FPGA's. Can you tell
me how to set static timing constraints on the pins that can only be
reached with IOB FFs?

Thanks & Regards,
Srini.