Make a signal free for glitches?

I have a CPU register block where I use the outputs (wich are supposed to be 
static) to control other clock domains.

The question rises; will these signals coming out of a flip-flop be 
guaranteed free for glitches?

For a synchronous design, there is a setup&hold condition in the cpu clock 
domain where this signal will be stable, but how about the rest of the time 
window? Is there any tricks to make this guaranteed glitch free?

The reason I ask is that I want to use this signal to mux (using 2 input 
muxcy to avoid lookup table glitches) a clock signal and I want the outgoing 
clk to be glitch-free. Maybe I have to route the switching signal thru a 
bidir pin and put a capacitor on it.

Note:I WILL treat this new clk as a new clock domain, and the domain WILL be 
reset properly after switching clock.

Morten Leikvoll schrieb:
> I have a CPU register block where I use the outputs (wich are supposed to be 
> static) to control other clock domains.
> 
> The question rises; will these signals coming out of a flip-flop be 
> guaranteed free for glitches?

The output of a flipflop is always glitch free (when setup and hold 
times are met)

> For a synchronous design, there is a setup&hold condition in the cpu clock 
> domain where this signal will be stable, but how about the rest of the time 
> window? Is there any tricks to make this guaranteed glitch free?
> 
> The reason I ask is that I want to use this signal to mux (using 2 input 
> muxcy to avoid lookup table glitches) a clock signal and I want the outgoing 
> clk to be glitch-free. Maybe I have to route the switching signal thru a 

This is another problem. In a tecXcluse a long time ago there was a 
glitch free clock MUX. They are also as hard macros in Virtex-II / 
Spartan 3 etc.

> bidir pin and put a capacitor on it.

Autsch. Dont do this! This is just a crude work around for, hmmmm,.
Dont do it!

Regards
Falk

There is a guaranteed glitch-free clock multiplexer design in "six easy
pieces", #6
Find it under TechXclusives on the Xilinx website, or click on:

http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
&sTechX_ID=pa_six_easy&languageID=1

Sorry for the ridiculously long URL.
Peter Alfke, Xilinx
===============
Morten Leikvoll wrote:
> I have a CPU register block where I use the outputs (wich are supposed to be
> static) to control other clock domains.
>
> The question rises; will these signals coming out of a flip-flop be
> guaranteed free for glitches?
>
> For a synchronous design, there is a setup&hold condition in the cpu clock
> domain where this signal will be stable, but how about the rest of the time
> window? Is there any tricks to make this guaranteed glitch free?
>
> The reason I ask is that I want to use this signal to mux (using 2 input
> muxcy to avoid lookup table glitches) a clock signal and I want the outgoing
> clk to be glitch-free. Maybe I have to route the switching signal thru a
> bidir pin and put a capacitor on it.
>
> Note:I WILL treat this new clk as a new clock domain, and the domain WILL be
> reset properly after switching clock.

Thanks for this solution! :) I still miss an explanation why the muxcy 
solution may fail, counting out the possible glitches at the point of 
switching, wich I intend to take care of using synchronous resets.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147718359.906533.179030@y43g2000cwc.googlegroups.com...
> There is a guaranteed glitch-free clock multiplexer design in "six easy
> pieces", #6
> Find it under TechXclusives on the Xilinx website, or click on:
>
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
> &sTechX_ID=pa_six_easy&languageID=1
>
> Sorry for the ridiculously long URL.
> Peter Alfke, Xilinx

On second thought.... Are you sure this is safe? What if the three right 
gates are implemented in a lookup table (they probably will, won't they)? 
Having 2 different clocks into a lookuptable sounds very risky for the 
output.

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147718359.906533.179030@y43g2000cwc.googlegroups.com...
> There is a guaranteed glitch-free clock multiplexer design in "six easy
> pieces", #6
> Find it under TechXclusives on the Xilinx website, or click on:
>
> http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
> &sTechX_ID=pa_six_easy&languageID=1
>
> Sorry for the ridiculously long URL.
> Peter Alfke, Xilinx
> ===============

I am sure it is safe. This circuit has proven to be glitchfree, as
described in the words around it (metastability lass than half a clock
period)
In general: Whenever you change one input of a LUT, there is no glitch
at the output if the two input addresses generate the same output
level.
I documented this 15 years ago...
Peter Alfke, Xilinx

Peter Alfke wrote:
> In general: Whenever you change one input of a LUT, there is no glitch
> at the output if the two input addresses generate the same output
> level.
> I documented this 15 years ago...

This information doesn't seem to have made it into the datasheets, which is
why I asked that question a few months ago.

Eric

This is what I wrote 15 yars ago, and it still applies:
"..Note that there can never be a decoding glitch when only one select
(address) input changes. (Even a non-overlapping decoder cannot
generate a glitch problem, since the node capacitance will retain the
previous logic level until the new pass gate is activated a fraction of
a nanosecond later)
When more than one input changes "simultaneously", the user must
analyze the logic output for any possible intermediate address code
permutation. If any of them would produce a different output, the user
must assume that a glitch might occur. If all of the possible address
variations produce the identical output, then the user can be sure that
there will be no glich at the output.

The designers of synchronous systems generally do not worry about such
glitches, since synchronous designs are inherently immune to data
glitches, except on clocks and asynchronous Set or reset inputs."

I hope this helps
Peter Alfke,  15 years later still at Xilinx...

Peter Alfke wrote:
> There is a guaranteed glitch-free clock multiplexer design in "six easy
> pieces", #6
> Find it under TechXclusives on the Xilinx website, or click on:
>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
> &sTechX_ID=pa_six_easy&languageID=1
>
> Sorry for the ridiculously long URL.
> Peter Alfke, Xilinx

It's not a very useful UR - generates following from Mozilla:

http://www.xilinx.com/tech_difficulties.htm
Sorry...
Technical difficulties with the Xilinx.com web site have been solved.
If you are continuing to have difficulty accessing Xilinx.com, you may
need to exit your browser software and restart it. Please accept our
apologies for any difficulties you have experienced.

obviously not solved :(

fpga_toys@yahoo.com wrote:
> Peter Alfke wrote:
> 
>>There is a guaranteed glitch-free clock multiplexer design in "six easy
>>pieces", #6
>>Find it under TechXclusives on the Xilinx website, or click on:
>>http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sGlobalNavPick=&sSecondaryNavPick=&category=-1211408&iLanguageID=1&multPartNum=1
>>&sTechX_ID=pa_six_easy&languageID=1
>>
>>Sorry for the ridiculously long URL.
>>Peter Alfke, Xilinx

> 
> 
> It's not a very useful UR - generates following from Mozilla:
> 
> http://www.xilinx.com/tech_difficulties.htm
> Sorry...
> Technical difficulties with the Xilinx.com web site have been solved.
> If you are continuing to have difficulty accessing Xilinx.com, you may
> need to exit your browser software and restart it. Please accept our
> apologies for any difficulties you have experienced.
> 
> obviously not solved :(

Seems to have moved to here ?
http://www.xilinx.com/xlnx/xweb/xil_tx_display.jsp?sTechX_ID=pa_six_easy&iLanguageID=1&iCountryID=1

-jg