Make a signal free for glitches?

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147896100.445238.78820@i39g2000cwa.googlegroups.com...
> This is what I wrote 15 yars ago, and it still applies:
> "..Note that there can never be a decoding glitch when only one select
> (address) input changes. (Even a non-overlapping decoder cannot
> generate a glitch problem, since the node capacitance will retain the
> previous logic level until the new pass gate is activated a fraction of
> a nanosecond later)
> When more than one input changes "simultaneously", the user must
> analyze the logic output for any possible intermediate address code
> permutation. If any of them would produce a different output, the user
> must assume that a glitch might occur. If all of the possible address
> variations produce the identical output, then the user can be sure that
> there will be no glich at the output.
>
> The designers of synchronous systems generally do not worry about such
> glitches, since synchronous designs are inherently immune to data
> glitches, except on clocks and asynchronous Set or reset inputs."
>
> I hope this helps
> Peter Alfke,  15 years later still at Xilinx...

Thanks a lot Peter. It DID help sort out this protential problem :)

Btw.. I compressed the URL at http://tinyurl.com/fufdt

their webmaster is on hawai vaccation as usual !

antti