Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be configured as a RAM64 or SRL32. But a CLB can only have 4 RAMs or SRLs (similar to SLICEL / SLICEM). DSP blocks have a 25x18 multiplier (useful for 32-bit floating point). Block RAMs are 36 kbits. Press release says engineering samples of LX50, lX85, LX110 are shipping now. LX50: 7,200 slices (actual slices, CLB array 120*30) 48 BRAMs (each 36kbits, total 1728 kbits) 48 DSP FF324, FF676, FF1153 LX85: 12,960 slices 96 BRAMs 48 DSP FF676, FF1153 LX110: 17,280 slices 129 BRAMs 64 DSP FF676, FF1153, FF1760 Press release http://www.xilinx.com/prs_rls/2006/silicon_vir/0658lxship.htm Slice schematics, some timing numbers and performance figures (PDF) http://www.xilinx.com/bvdocs/whitepapers/wp245.pdf Product table, (slice/bram/dsp/io counts for each LX-series part) (PDF) http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/Virtex-5_LX_Product_Table.pdf Comparison with Virtex-4 http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/overview/v5v4features.htm
Virtex 5 announced
Started by ●May 15, 2006
Summary
Xilinx representatives and community members discuss the official announcement and technical specifications of the Virtex-5 FPGA family.
Xilinx representatives and community members discuss the official announcement and technical specifications of the Virtex-5 FPGA family. The discussion focuses on the architectural shift from 4-input to 6-input LUTs and the move to a 65nm triple-oxide manufacturing process.
Key details emerge regarding software support schedules in ISE 8.2i, the performance benefits of reduced logic levels, and the roadmap for upcoming LX, LXT, and FX variants.
- The 6-input LUT architecture provides an average 30% speedup over Virtex-4 by reducing logic levels and interconnect overhead.
- Virtex-5 utilizes a 65nm triple-oxide process to optimize for stability, low leakage, and reduced dynamic power.
- Initial software support for Virtex-5 LX parts is scheduled for ISE 8.2i, with the system monitor block present in silicon but pending software enablement.
- DSP blocks have been updated to a 25x18 multiplier configuration to better support 32-bit floating point operations.
- The 6-input LUT is implemented as a true 64-bit look-up table, though documentation may represent it as two 5-input LUTs for tutorial purposes.
Xilinx Virtex-5FPGA Architecture6-LUTHardware Specifications
Reply by ●May 15, 20062006-05-15
ryanrs, Yup. Now Peter and I are able to talk about Virtex 5. Any questions? 65nm lives....both fabs! Of course, it is early, but we are in ES sampling, and accepting folks for early adoption. The release of the documention should be pretty good. I'd like to hear back on how good folks think it is. Austin ryanrs wrote:> Two slices per CLB, four 6-LUTs + 4 FFs per slice. A LUT can be > configured as a RAM64 or SRL32. But a CLB can only have 4 RAMs or SRLs > (similar to SLICEL / SLICEM). DSP blocks have a 25x18 multiplier > (useful for 32-bit floating point). Block RAMs are 36 kbits. > > Press release says engineering samples of LX50, lX85, LX110 are > shipping now. > > LX50: > 7,200 slices (actual slices, CLB array 120*30) > 48 BRAMs (each 36kbits, total 1728 kbits) > 48 DSP > FF324, FF676, FF1153 > > LX85: > 12,960 slices > 96 BRAMs > 48 DSP > FF676, FF1153 > > LX110: > 17,280 slices > 129 BRAMs > 64 DSP > FF676, FF1153, FF1760 > > Press release > http://www.xilinx.com/prs_rls/2006/silicon_vir/0658lxship.htm > > Slice schematics, some timing numbers and performance figures (PDF) > http://www.xilinx.com/bvdocs/whitepapers/wp245.pdf > > Product table, (slice/bram/dsp/io counts for each LX-series part) (PDF) > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/Virtex-5_LX_Product_Table.pdf > > Comparison with Virtex-4 > http://www.xilinx.com/products/silicon_solutions/fpgas/virtex/virtex5/overview/v5v4features.htm >
Reply by ●May 15, 20062006-05-15
On Mon, 15 May 2006 09:49:53 -0700, Austin Lesea wrote:> ryanrs, > > Yup. Now Peter and I are able to talk about Virtex 5. > > Any questions? > > 65nm lives....both fabs! > > Of course, it is early, but we are in ES sampling, and accepting folks for > early adoption. > > The release of the documention should be pretty good. I'd like to hear > back on how good folks think it is. > > Austin > >I don't see any mention of a V5FX on your website. Can you tell us anything about the RocketIO on the Virtex5-FX yet?
Reply by ●May 15, 20062006-05-15
Josh, Always ask for what we didn't release? OK, that is fair. I wasn't very specific. Details on FX in June. For now, questions on LX. Austin Josh Rosen wrote:> On Mon, 15 May 2006 09:49:53 -0700, Austin Lesea wrote: > > >>ryanrs, >> >>Yup. Now Peter and I are able to talk about Virtex 5. >> >>Any questions? >> >>65nm lives....both fabs! >> >>Of course, it is early, but we are in ES sampling, and accepting folks for >>early adoption. >> >>The release of the documention should be pretty good. I'd like to hear >>back on how good folks think it is. >> >>Austin >> >> > > > I don't see any mention of a V5FX on your website. Can you tell us > anything about the RocketIO on the Virtex5-FX yet? > >
Reply by ●May 15, 20062006-05-15
I like the price of the eval boards!! 0.00 USD published price on Xilinx web!! but well not available, guess the S3, S3E SAD STORY is repeating again or can we hope for better availability ?? hm the 0.00 USD price is eval without the Virtex-5 you have pictures of the boards, and still not available, what could be the reason for not selling eval boards that are made without the silicon? must be some reason. at least there is an v5 LX on the eval board picture :) Antti
Reply by ●May 15, 20062006-05-15
Reply by ●May 15, 20062006-05-15
I am trying to be fair now, only asking LX questions :) 1) Xilinx website says to the general public that 'start designing' NOW to my understanding it means that software support is available NOW, or is there is any other way to see it? 2) the sysmonitor and ADC block that is present in V4 silicon but disabled by the design software, it is ripped out from V5 ? hm, I am afraid all my others questions are related to FX so it would be fair to ask those. grrrr Antti Lukats PS ROTFL ROTFL ROTFL - this is was gooood laugh !!!! I had to re-register again to gain access to the support archive for the V5 user guide. The download size was indicated as 9MB, made me interested what the heck is inside, NOW I know: the 9MB archive holds a single file, with famous name: readme.txt --------------- This is a placeholder file for the Virtex-5 SSO calculator. The calculator is due to be available with ISE8.2i software. --------------- Hm at least it's now clear that V5 support must be included in ISE 8.2i and not 9.x ? Or will 8.2i only include that SSO Calculator?? But then what and when will actual V5 support be included in ISE/EDK? Anayway it was good ROTFL ! ! ! The office is empty so I had no fear anyone calling the 911
Reply by ●May 15, 20062006-05-15
Hi Austin, This gives me the impression that V4-FX will be skipped - or at least customers will be pushed to V5-FX. This scares me quite a lot, actually. OK, now some questions for the LX: How does the performance compares with V4-LX for simple things like Counter/Mux/Booth Multiplier. Any trade-offs for the I/O? Full 3.3V tolerant/compatible? What's the core voltage? That's it for now. I look forward to get hands on the (prelim.) datasheet. Regards and thanks for you response, Luc On Mon, 15 May 2006 10:19:20 -0700, Austin Lesea <austin@xilinx.com> wrote:>Josh, > >Always ask for what we didn't release? OK, that is fair. I wasn't very >specific. > >Details on FX in June. > >For now, questions on LX. > >Austin > >Josh Rosen wrote: > >> On Mon, 15 May 2006 09:49:53 -0700, Austin Lesea wrote: >> >> >>>ryanrs, >>> >>>Yup. Now Peter and I are able to talk about Virtex 5. >>> >>>Any questions? >>> >>>65nm lives....both fabs! >>> >>>Of course, it is early, but we are in ES sampling, and accepting folks for >>>early adoption. >>> >>>The release of the documention should be pretty good. I'd like to hear >>>back on how good folks think it is. >>> >>>Austin >>> >>> >> >> >> I don't see any mention of a V5FX on your website. Can you tell us >> anything about the RocketIO on the Virtex5-FX yet? >> >>
Reply by ●May 15, 20062006-05-15
Antti, LXT is the LX with transceivers, yes. We have not finished with the characterization of the transceivers. Stay tuned for their announcement. Austin Antti wrote:> does LXT is include rocket IO? > > ok, I am not fair - you specified LX not LXT > > Antti >
Reply by ●May 15, 20062006-05-15
Antti,> 1) Xilinx website says to the general public that 'start designing' NOW > to my understanding it means that software support is available NOW, or > is there is any other way to see it?Software is available now.> 2) the sysmonitor and ADC block that is present in V4 silicon but > disabled by the design software, it is ripped out from V5 ?It will be back, but not right away (in the software, it is definitely there in V5). Some things require a lot of characterization, and yield analysis, and we do not want to put customrs through what we did last time, for which we are very sorry, and promised not to do again. We did get the sysmon working in V4, but too late to introduce it. It did allow us to debug the process of testing, yielding, etc. a complex analog block. What we learned was applied to V5.> hm, I am afraid all my others questions are related to FX so it would > be fair to ask those. grrrrSorry. FX comes later. Transceivers come later, LXT. But the LXT will be here sooner than the FX or FXT parts.> readme.txt > --------------- > This is a placeholder file for the Virtex-5 SSO calculator. The > calculator is due to be available with ISE8.2i software. > ---------------The SSO calculator just missed by hours for this deadline. Try the link tomorrow. It was just one of those things where the key person who we needed to get us the numbers was out on vacation until last Monday, so we didn't have all the time we thought we had to get it ready.> Hm at least it's now clear that V5 support must be included in ISE 8.2i > and not 9.x ?Yes.> Or will 8.2i only include that SSO Calculator?? But then what and when > will actual V5 support be included in ISE/EDK?No, SSO will be there very shortly. ISE/EDK is another matter. I don't know the schedule on that. For Microblaze, that should be now (or very soon). For PPC, that waits for the FX. Maybe someone who knows will email me. Austin
