Virtex 5 announced

John_H wrote:

> Kudos on the new release!
> 
> But I started to glaze over as you turned on your marketing engines.  I 
> sincerely prefer the technical Austin.

Yes, but this Austin can still be entertaining, as he waves his arms  :)

eg  I'm looking forward to just what exactly "equivalent static power"
can be ?

  Could that be like their equivalent LUTs, perhaps ?

-jg

Austin Lesea <austin@xilinx.com> wrote:
...
> Imitation is the sincerest form of flattery, as STM now also has a 
> triple oxide 90nm process.  I am sure they will also offer it at 65nm, 
> as they also realized how useful it was to their customers.

If using triple oxide is imitation and "Imitation is the sincerest form of
flattery" then the whole semiconductor industry is using this
"flattery". Did Xilinx invent the MOS transistor, self aligning gates, wire
bonding, etc. and all those other things they use to produce an IC?  Well,
as Newton said: "If I have seen a little further it is by standing on the
shoulders of Giants."

Is using a third oxid thickness really that great genuine invention nobody
thought of before. Didn't the engineers at Xilinx need to bang their head
fighting for this feature against many (d|m)amages seeing only the added
cost? Perhaps other engineers in other companies wheren't that succesfull on
the first try. Now perhaps their (d|m)amages see the light.

Otherwise congratulation to the new "baby".

And hopefully a faster release story to general availability then for 
XC3SE and ... and ...

Cheers
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

As far as chip area goes, the decision to go to LUT6 (as we call it)
was a no-brainer:

Extensive benchmarking shows that a LUT6 is 'worth" about 1.4 LUT4
(this is an average over almost 200 designs, your mileage may vary...)
Our designers found that the CLB size penalty for LUT6 compared to
using LUT4 in the same technology is only about 15% (Yes, the LUT takes
only a small portion of the silicon area)

Gaining 40% in functional density for a 15% price in larger area is, of
course, a win-win situation.
The higher performance due to fewer levels of LUTs and reduced
interconnects is just a bonus. Nice bonus, thank you!
Peter Alfke, Xilinx

"Ed McGettigan" <ed.mcgettigan@xilinx.com> schrieb im Newsbeitrag 
news:4468D3A2.7040600@xilinx.com...
> Antti wrote:
>> the basic LUT delay cant be much faster, it was pretty damn fast in V4 
>> already !
>> however the 6 input LUT is not true 6 input LUT but two 5 input LUTs and 
>> a mux
>> so if the mux delay is significant then 6 input function will we way 
>> slower than
>> 5 input function, sure there is still performance gain over plain 4 LUT
>> architecture.
>
> The Virtex-5 6-input LUT is a true 64-bit look-up-table.  Any 6 input
> function can be implemented in the LUT.  You can of course think of
> any LUT as being generated a 128-to-1 MUX, but that would be inefficient
> in actual hardware to build.
>
> As for the timing, the Virtex-5 data sheet is online with timing
> delays for all three speed grades so you can verify the performance
> differences.
>
> Ed McGettigan
> --
> Xilinx Inc.

Hi Ed,

well if you say so, but the datasheet shows

2 separate 5 input LUTs
1 output select MUX that combines the makes the 5 input LUTs to look like 
one 6 input LUT

if I look at that schematic from the datasheet then the 6 input function 
would include
LUT delay and MUX in series.

if you say it is not 2 LUTs and 1 MUX, but one LUT,
well then is the datasheet really confusing!!

Antti 

"Kolja Sulimma" <news@sulimma.de> schrieb im Newsbeitrag 
news:4468d210$0$11063$9b4e6d93@newsread4.arcor-online.net...
> Antti schrieb:
>
>> however the 6 input LUT is not true 6 input LUT but two 5 input LUTs
>> and a mux
>> so if the mux delay is significant then 6 input function will we way
>> slower than
>> 5 input function, sure there is still performance gain over plain 4 LUT
>> architecture.
>
> Hmm. There really is no difference between a MUX and a LUT.
> Same schematic symbol, same choice of implementations, same thing.
>
>> the basic LUT delay cant be much faster, it was pretty damn fast in V4
>> already !
>
> You can not really read the circuit speed from the datasheet or FPGA
> editor, as they use abstracted timing models.
> You can push delay around almost at will in a timing model.
> At any node of the timing model you can subtract a delay from all
> outgoing edges and add them to all incoming edges without changing the
> model. If you reduce the delay of some edges to zero you can merge
> nodes. You can even have negative delay edges in timing models.
>
> You can use this to simplify the model for your software or for the
> user. Or you can try to look better than your competitor this way
> because people tend to compare certain delays and ignore others.
>
> As a note: The value for the carry chain is pretty reliable beacuse each
> element is immediately preceeded and succeeded by an identical element.
> Not much pushing possible there.
>
> Kolja Sulimma
Hi Kolja

I am referring to my results of actual LUT delay measurements.
what I did before looking the datasheet info. I was almost not
to belive the lut delay (too small!) in V4. Only after seeing
it in real silicon i looked up the timing info in datasheet.

Antti

Austin Lesea wrote:
> lb,
>
> V4 FX is not skipped.  It is most definitely being shipped right now.
> In fact the backlog was just cleared.
> 

Are any FX40 parts at the fab yet?

Cheers,
Jon

Antti, remember how a LUT is really constructed.
It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
christmas tree.
The data sheet just (for tutorial purposes) shows the final stage of
this big multiplexer separately.
If that bothers you, ignore it. But just do not believe that it costs
more than the extra delay of any multiplexer level.
There are 6 levels of multiplexing, nothing we can do about it.
Peter Alfke

Quoth Uwe:

> Well, as Newton said: "If I have seen a little further it is by
> standing on the shoulders of Giants."

... yeah, but oft-forgotten is that Newton was being a dick. He wrote
that in a letter to Hooke, who was notoriously short of stature, while
they were arguing over who was the first for some discovery or other...


It's often quoted as if Newton was being humble, but what he was saying
was "I'm better than you, and nothing you have done was remotely useful
to science"...

Simon

Jim,

Basically, equivalent in this sense is "equal."

So if the static power was 1 watt before, it is still one watt (or less).

At 65nm, there is gate leakage.

Gate leakage does not vary with temperature.

So there is a component of the static power that remains the same at 
-40C, or at 25C, or even at 100C.

That factor is a significant part of the static leakage.  Basically, the 
cost of using 65nm.

What you will find is that the typical static current for Vccint 
(Iccint) for V5 is at first, larger than what you would expect. 
However, it will be on par, or below what the 100C number was for the 
V4.  If the worst case for V4 at 100C was X watts, then a similar sized 
V5 will be X watts or less over the entire tempeature range, without a 
huge difference from 25C to 100C (which was what folks are used to 
seeing before gate leakage became a dominant factor in 65nm).

Does this answer the question?

Austin

Jim Granville wrote:

> John_H wrote:
> 
>> Kudos on the new release!
>>
>> But I started to glaze over as you turned on your marketing engines.  
>> I sincerely prefer the technical Austin.
> 
> 
> Yes, but this Austin can still be entertaining, as he waves his arms  :)
> 
> eg  I'm looking forward to just what exactly "equivalent static power"
> can be ?
> 
>  Could that be like their equivalent LUTs, perhaps ?
> 
> -jg
> 

Uwe,

Easy for you to say now.  But there was a time where the competition was 
selling against triple oxide as being too new, too risky, and too 
expensive (with no benefit).

So, humor me, name the chips that use a triple oxide process.

Austin

Uwe Bonnes wrote:

> Austin Lesea <austin@xilinx.com> wrote:
> ...
> 
>>Imitation is the sincerest form of flattery, as STM now also has a 
>>triple oxide 90nm process.  I am sure they will also offer it at 65nm, 
>>as they also realized how useful it was to their customers.
> 
> 
> If using triple oxide is imitation and "Imitation is the sincerest form of
> flattery" then the whole semiconductor industry is using this
> "flattery". Did Xilinx invent the MOS transistor, self aligning gates, wire
> bonding, etc. and all those other things they use to produce an IC?  Well,
> as Newton said: "If I have seen a little further it is by standing on the
> shoulders of Giants."
> 
> Is using a third oxid thickness really that great genuine invention nobody
> thought of before. Didn't the engineers at Xilinx need to bang their head
> fighting for this feature against many (d|m)amages seeing only the added
> cost? Perhaps other engineers in other companies wheren't that succesfull on
> the first try. Now perhaps their (d|m)amages see the light.
> 
> Otherwise congratulation to the new "baby".
> 
> And hopefully a faster release story to general availability then for 
> XC3SE and ... and ...
> 
> Cheers