Virtex 5 announced

"Peter Alfke" <peter@xilinx.com> schrieb im Newsbeitrag 
news:1147725970.779784.92570@u72g2000cwu.googlegroups.com...
> Antti, remember how a LUT is really constructed.
> It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
> christmas tree.
> The data sheet just (for tutorial purposes) shows the final stage of
> this big multiplexer separately.
> If that bothers you, ignore it. But just do not believe that it costs
> more than the extra delay of any multiplexer level.
> There are 6 levels of multiplexing, nothing we can do about it.
> Peter Alfke
>

Hi Peter,

in LUT4 world the mux that allows the LUT4 to be used 5 input function DOES 
add extra delay compared to plain LUT4 delay IMHO

if the MUX in datasheet that is drawn 'for tutorial purposes' allows the 
LUT6 to be as fast as LUT5 that doesnt use that final MUX, then ok.

I was blindly assuming that component drawn as MUX does add extra delay when 
it is included in signal path, versus timing where signal bypasses it.

as V5 can implement SRL32 and not SRL64 then IMHO it is clear that LUT6 is 
made up from 2 LUT5 exactly as it is drawn in the datasheet.

Antti 

"Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
news:4468f4b4@clear.net.nz...
> Peter Alfke wrote:
>
>> Antti, remember how a LUT is really constructed.
>> It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
>> christmas tree.
>> The data sheet just (for tutorial purposes) shows the final stage of
>> this big multiplexer separately.
>> If that bothers you, ignore it. But just do not believe that it costs
>> more than the extra delay of any multiplexer level.
>> There are 6 levels of multiplexing, nothing we can do about it.
>
> ISTR that Altera define differing delay times, for their LUT inputs.
> Will Xilinx define to that level of detail now, as well ?
>
> -jg
>
yes Altera uses different LUT delays for different inputs to achive better 
timing

Antti 

Peter Alfke wrote:

> Antti, remember how a LUT is really constructed.
> It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
> christmas tree.
> The data sheet just (for tutorial purposes) shows the final stage of
> this big multiplexer separately.
> If that bothers you, ignore it. But just do not believe that it costs
> more than the extra delay of any multiplexer level.
> There are 6 levels of multiplexing, nothing we can do about it.

ISTR that Altera define differing delay times, for their LUT inputs.
Will Xilinx define to that level of detail now, as well ?

-jg

Jon,

The 4VFX40 and FX140 were taped out, with first samples available 4th Q 
2006.

I would suggest using the FX60 for development for a FX40 design.

Check with your FAE for status.  But now that we have fixed things, 
these should go smoothly.

Sadly, the fixes to the MGTs did affect the timeliness of the rollout 
(an understatement if I have ever made one).  Let us be honest;  IT MADE 
US LATE!  YES, L A T E.

And we are very sorry, and we promise not to ever make those mistakes again.

All the other parts (FX12, 20, 60, 100) are available as 'CES4'.

If anyone wants to berate us for their FX experience on V4, please do 
(we deserve it).  All I can say is that we have finally fixed things, 
and are shipping, and will go to production now that we have that over 
and done with.

 From the lash marks on the senior execs, I'd say our customers were 
very expressive with their displeasure, and a lot of processes and 
procedures got changed when it comes to announcing anything.  Especially 
anything with analog content.  We also have learned a lot about making 
gigabit transceivers that will work flawlessly, work identically, and 
yield well.

Austin



Jon Beniston wrote:

> Austin Lesea wrote:
> 
>>lb,
>>
>>V4 FX is not skipped.  It is most definitely being shipped right now.
>>In fact the backlog was just cleared.
>>
> 
> 
> Are any FX40 parts at the fab yet?
> 
> Cheers,
> Jon
> 

Antti,

So do we.

Austin

Antti Lukats wrote:

> "Jim Granville" <no.spam@designtools.co.nz> schrieb im Newsbeitrag 
> news:4468f4b4@clear.net.nz...
> 
>>Peter Alfke wrote:
>>
>>
>>>Antti, remember how a LUT is really constructed.
>>>It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
>>>christmas tree.
>>>The data sheet just (for tutorial purposes) shows the final stage of
>>>this big multiplexer separately.
>>>If that bothers you, ignore it. But just do not believe that it costs
>>>more than the extra delay of any multiplexer level.
>>>There are 6 levels of multiplexing, nothing we can do about it.
>>
>>ISTR that Altera define differing delay times, for their LUT inputs.
>>Will Xilinx define to that level of detail now, as well ?
>>
>>-jg
>>
> 
> yes Altera uses different LUT delays for different inputs to achive better 
> timing
> 
> Antti 
> 
> 

On Mon, 15 May 2006 14:48:26 -0700, Austin Lesea wrote:

> Jon,
> 
> The 4VFX40 and FX140 were taped out, with first samples available 4th Q
> 2006.
> 
> I would suggest using the FX60 for development for a FX40 design.
> 
> Check with your FAE for status.  But now that we have fixed things, these
> should go smoothly.
> 
> Sadly, the fixes to the MGTs did affect the timeliness of the rollout (an
> understatement if I have ever made one).  Let us be honest;  IT MADE US
> LATE!  YES, L A T E.
> 
> And we are very sorry, and we promise not to ever make those mistakes
> again.
> 
> All the other parts (FX12, 20, 60, 100) are available as 'CES4'.
> 
> If anyone wants to berate us for their FX experience on V4, please do (we
> deserve it).  All I can say is that we have finally fixed things, and are
> shipping, and will go to production now that we have that over and done
> with.
> 
>  From the lash marks on the senior execs, I'd say our customers were
> very expressive with their displeasure, and a lot of processes and
> procedures got changed when it comes to announcing anything.  Especially
> anything with analog content.  We also have learned a lot about making
> gigabit transceivers that will work flawlessly, work identically, and
> yield well.
> 
> Austin

Originally the V4FX series was supposed to support quad date rate (10GHz),
is that ever going to happen or has Xilinx given up on that? In the
InfiniBand world QDR is going to start happening in the 2007 time frame so
it would be nice if QDR RocketIO were to become available next year in
either the V4FX or V5FX.

Also do you plan to add hardware CRC16s to the V5FX? The V4FX had hardware
CRC32s but not CRC16s, having both would be a big help. 

One final thing which is a tools issue and has nothing to do with the
hardware. Please provide separate models for the CRC32s, tying them to the
RocketIO models is a major pain. The CRC32 may be physically located in
the same tile as the SerDes but logically it's independent. It makes as
little sense to combine the CRC32 model with the SerDes model as it would
to tie the Block RAM and Multiplier together. Those components are also
next to each other but you provide separate models. One final thing,
please provide Verilog behavioral models for the RocketIO instead of those
awful SMART models. SMART models slow down the simulation and their lack
of transparency complicates the debug process.

 

Austin Lesea wrote:

> Jim,
> 
> Basically, equivalent in this sense is "equal."
> 
> So if the static power was 1 watt before, it is still one watt (or less).
> 
> At 65nm, there is gate leakage.
> 
> Gate leakage does not vary with temperature.
> 
> So there is a component of the static power that remains the same at 
> -40C, or at 25C, or even at 100C.
> 
> That factor is a significant part of the static leakage.  Basically, the 
> cost of using 65nm.
> 
> What you will find is that the typical static current for Vccint 
> (Iccint) for V5 is at first, larger than what you would expect. However, 
> it will be on par, or below what the 100C number was for the V4.  If the 
> worst case for V4 at 100C was X watts, then a similar sized V5 will be X 
> watts or less over the entire tempeature range, without a huge 
> difference from 25C to 100C (which was what folks are used to seeing 
> before gate leakage became a dominant factor in 65nm).
> 
> Does this answer the question?

Yes, thanks.
  I'll admit I took the 'Lower' in your sentence

" Lower dynamic power, and equivalent static power, today."

  as applying to all clauses.

  I do see the curves and infos, are rather sparse on revealing the 
_actual_ Static Icc numbers - as dynamic Icc keeps improving, the static
Icc is going to become a larger % of the power budget....

-jg

http://www.google.com/search?hl=en&lr=&q=%22triple+oxide%22+semiconductor+-xilinx

"Austin Lesea" <austin@xilinx.com> wrote in message 
news:e4arf0$avv12@xco-news.xilinx.com...
> Uwe,
>
> Easy for you to say now.  But there was a time where the competition was 
> selling against triple oxide as being too new, too risky, and too 
> expensive (with no benefit).
>
> So, humor me, name the chips that use a triple oxide process.
>
> Austin
>
> Uwe Bonnes wrote:
>
>> Austin Lesea <austin@xilinx.com> wrote:
>> ...
>>
>>>Imitation is the sincerest form of flattery, as STM now also has a triple 
>>>oxide 90nm process.  I am sure they will also offer it at 65nm, as they 
>>>also realized how useful it was to their customers.
>>
>>
>> If using triple oxide is imitation and "Imitation is the sincerest form 
>> of
>> flattery" then the whole semiconductor industry is using this
>> "flattery". Did Xilinx invent the MOS transistor, self aligning gates, 
>> wire
>> bonding, etc. and all those other things they use to produce an IC? 
>> Well,
>> as Newton said: "If I have seen a little further it is by standing on the
>> shoulders of Giants."
>>
>> Is using a third oxid thickness really that great genuine invention 
>> nobody
>> thought of before. Didn't the engineers at Xilinx need to bang their head
>> fighting for this feature against many (d|m)amages seeing only the added
>> cost? Perhaps other engineers in other companies wheren't that succesfull 
>> on
>> the first try. Now perhaps their (d|m)amages see the light.
>>
>> Otherwise congratulation to the new "baby".
>>
>> And hopefully a faster release story to general availability then for 
>> XC3SE and ... and ...
>>
>> Cheers 

"Peter Alfke" <peter@xilinx.com> wrote in message 
news:1147725970.779784.92570@u72g2000cwu.googlegroups.com...
> Antti, remember how a LUT is really constructed.
> It contains 64 latches plus a 6-level 64-to-1 multiplexer, like a
> christmas tree.
> The data sheet just (for tutorial purposes) shows the final stage of
> this big multiplexer separately.
> If that bothers you, ignore it. But just do not believe that it costs
> more than the extra delay of any multiplexer level.
> There are 6 levels of multiplexing, nothing we can do about it.
> Peter Alfke

So the luts are actually full multiplexers, not a memory array style of 
addressing?  I would have thought LUTs would work much better than general 
multiplexors by using a nand/nand style of structure to drive one active 
line in a 64-wide CMOS tree.  Muxes? 

Jim, the short answer is yes, and even for Virtex-4.
There is a limit to the numbers given in the data sheet, but Xilinx
software has, for several years, documented (and has taken advantage
of)  the differences in LUT through delay from the various inputs.  In
the battle of picoseconds, these small delay differences become
important

To Antti: The reason for only 32 bits in the SRL32, even though the
LUT6 has 64 latches, is different:
In previous generations with SRL16 in a LUT4, we used a circuit trick
(capacitive storage) to avoid using a master latch plus a slave latch,
which is the conventional way to build flip-flops or registers, even
shift registers. For ever smaller transistor geometries, such
"old-fashioned tricks" do not scale well, and we went back to a
conventional register implementation, with two latches per flip-flop,
thus only 32 shift register bits in a LUT6.

Thanks for the interest in Virtex-5. We are all very excited about our
new and very healthy baby... 
Peter Alfke,