Virtex 5 announced

Peter Alfke wrote:
> Jim, the short answer is yes, and even for Virtex-4.
> There is a limit to the numbers given in the data sheet, but Xilinx
> software has, for several years, documented (and has taken advantage
> of)  the differences in LUT through delay from the various inputs.  In
> the battle of picoseconds, these small delay differences become
> important
> 
> To Antti: The reason for only 32 bits in the SRL32, even though the
> LUT6 has 64 latches, is different:
> In previous generations with SRL16 in a LUT4, we used a circuit trick
> (capacitive storage) to avoid using a master latch plus a slave latch,
> which is the conventional way to build flip-flops or registers, even
> shift registers. For ever smaller transistor geometries, such
> "old-fashioned tricks" do not scale well, and we went back to a
> conventional register implementation, with two latches per flip-flop,
> thus only 32 shift register bits in a LUT6.
> 
> Thanks for the interest in Virtex-5. We are all very excited about our
> new and very healthy baby... 
> Peter Alfke,

  When will this topology be available in Spartan families ?

-jg

I can use google, too.

None of these links are actually referring to a real product, and most 
are referring to Xilinx (without naming us, like the Altera quote).

Austin

> http://www.google.com/search?hl=en&lr=&q=%22triple+oxide%22+semiconductor+-xilinx

John_H schrieb:
> "Peter Alfke" <peter@xilinx.com> wrote in message 

>>There are 6 levels of multiplexing, nothing we can do about it.
>>Peter Alfke
> 
> 
> So the luts are actually full multiplexers, not a memory array style of 
> addressing?  I would have thought LUTs would work much better than general 
> multiplexors by using a nand/nand style of structure to drive one active 
> line in a 64-wide CMOS tree.  Muxes? 

In a RAM you can reuse the decoder logic over many bitlines.
For a single bit output adress decoders are larger, slower and have
higher capacitance compared to pass transistor muxes.
Maybe there is a sweet spot a little off from the extreme so maybe the
tree has one or two levels less and uses one input as enable (or
wordline if you like). But I am sure  that most of it is a tree of pass
transistors....
After all the technology used is highly optimized for pass transistors.

Also:
A MUX build with address decoders enabling a common bitline is still a
MUX...

Kolja Sulimma

Hi Austin,

LX datasheets says up to 10 DSP48E colums per device, but the largest
of the LX family, LX330 only has 2 not 10 DSP48E columns?

Are devices that actually have 10 columns already planned?
Scary to think how larger would the be!

Antti

Hi Peter,

interesting, as much as I recall at the time Altera was claiming to
support
LUT input delay difference in their tools, Xilinx had no public info
that the
input delay are different or that they are actually calculated
compensated
in Xilinx software.

"documented" in your wording means that this behaviour of Xilinx
software
was documented for the user of the software or that it internally uses
it?

oh well if it that info has been available earlier I have missed it
(I am not so good doing that RTFM thing sometimes)

and sure the last picosends do count also!

Antti

Antti,
The numbers for the LUT delay differences from the various inputs are
not in the data sheet, but they are (and have been for years) in the
speeds files used by the software, and are (and have been) thus also
reported in any performance reports.
Regarding the DSP columns, I do not know where you read the number 10
(please tell me so we can fix that mistake).
Far more relevant is the number of such slices, and the max is 192 in
the 5VLX330.

Peter Alfke

ug193 page 13

"Virtex-5 family members have one, two, six, or ten DSP48E columns."

Antti, that's what happens when we release a family in several
installments.
As you can imagine, there will be an "SX" subfamily, and it will have
more DSP columns, up to ten.
Now you guys know one more deep secret...
Peter Alfke

I did guess that actually. Well the logic in SX doesnt scale with the
DSP columns, but still it will be heavy crunching engine :)

Antti

We are currently planning on the V4 SX55, but really could use more speed, 
pins, MACs and less power.  Looks like the speed increases slightly, 
possibly more with the rearranged MAC; the power is down, that's good; will 
there be an increase in the MACs and pins available?  Any indication of a 
release date for samples?
Marco
________________________
Marc Reinig
UCO/Lick Observatory
Laboratory for Adaptive Optics