Virtex 5 announced

Paul Leventis wrote:
> Hi Antti,
> 
> No comment means that we could be coming out any time.
> 
> Max II is pretty awesome in many ways (performance, cost per logic
> function, etc.)  

  Yes, cost/FF is ok, but the 'cost/size of the smallest device' have 
taken quite a hike with this family.
  So it missed quite a large chunk of 7000 and 3000 markets.

Leaves AnaChip, Atmel, Lattice, Xilinx in the low power, small package 
arena.


> There are some applications where non-volatility and
> RAM would be handy, and these aren't addressed by Max II.  We've got
> that feedback and will factor it into future architecture decisions --
> but its always a trade-off of the cost (die-size impact) of adding
> additional features vs. the size of the market that those additional
> features will open to us.

You could always just admit it was an oversight, instead of using 40 odd
words to say the same thing... :)

-jg

Antti wrote:

> hm to my understanding the V4 MGT are stripped down from original spec
> (10G) to meat the serdes in Stratix-IIGX ? So where do the V4 serdes
> beat SII-GX ? Perhaps they do, but for me it's not so obvious (not
> since the virtex 10G rocketio is "taken out" from V2Pro-X and V4).

I've missed the twists and turns of the SERDES/MGT saga.

I would be grateful if someone could briefly summarise what was promised in 
the various product generations and what was (eventually) provided. 

WAS
===================================
V2Pro-X (highest speed grade only!) - 10GB/s
V4FX - 10GB/s

REALITY
===================================
V2Pro-X highes speed grade - not available any more
V4 spec reduced to 6.x GB/s
V5 spec also 6.x GB/s

that how I understand the "saga"

Antti

Paul Leventis wrote:
> Hi Antti,
> 
> No comment means that we could be coming out any time.
> 
> Max II is pretty awesome in many ways (performance, cost per logic
> function, etc.).  There are some applications where non-volatility and
> RAM would be handy, and these aren't addressed by Max II.  We've got
> that feedback and will factor it into future architecture decisions --
> but its always a trade-off of the cost (die-size impact) of adding
> additional features vs. the size of the market that those additional
> features will open to us.
> 

A couple of RAM banks and a PLL would make all the difference to the MaxII.

I'd also add 5V tolerant inputs, and smaller/cheaper versions to a wish 
list, if you making a collection.

mvh.,

David



> Regards,
> 
> - Paul
> 

Antti wrote:
<snip>
> PS hope you guy fixup the mockup with MAX2, I mean machXO beats MAX2
> hands down, not that MAX2 is bad, it's pretty nice, but.. no RAM is a
> real issue

  I see today QuickLogic are ramping their PolarPro devices :
Claim appx $2.95 (in the mythical 'high volume' ) for the 640 register 
device.

  These devices DO have RAM and also FIFO controllers

  So they go up against the MAX II and Mach XO,
(but are, of course, OTP - what you gain is low static Icc)

  Still you could develop using MachXO and then consider a move to 
PolarPro, if the Lattice devices are too hungry, or too expensive... ?

-jg

Jim Granville <no.spam@designtools.co.nz> writes:
>   I see today QuickLogic are ramping their PolarPro devices :
> Claim appx $2.95 (in the mythical 'high volume' ) for the 640 register
> device.

Looks great for low-power applications!  But I was surprised to be
completely unable to find a list of their distributors on the QuickLogic
web site.  How do they expect to sell any parts?

Any idea of the cost of the development software?

It was also unclear to me whether the parts can be programmed in-circuit
(though of course only once), or whether they have to be programmed by a
standalone programmer before they are soldered down.

Peter Alfke wrote:
> As far as chip area goes, the decision to go to LUT6 (as we call it)
> was a no-brainer:
> 
> Extensive benchmarking shows that a LUT6 is 'worth" about 1.4 LUT4
> (this is an average over almost 200 designs, your mileage may vary...)
> Our designers found that the CLB size penalty for LUT6 compared to
> using LUT4 in the same technology is only about 15% (Yes, the LUT takes
> only a small portion of the silicon area)
> 
> Gaining 40% in functional density for a 15% price in larger area is, of
> course, a win-win situation.
> The higher performance due to fewer levels of LUTs and reduced
> interconnects is just a bonus. Nice bonus, thank you!
> Peter Alfke, Xilinx
> 
Well, it isn't exactly free.  You do take a hit in the LUT performance, 
which as you point out is actually a win *IF* the design would have gone 
to two levels of logic with only a 4-LUT.  The fact of the matter is, as 
a high performance system designer, I specifically design my logic so 
that it has only one layer of logic between FF's.  With that in mind, 
then assuming all else is equal, the 6-LUT represents a decrease in 
absolute clock performance. In the case of V5, that hit is hidden with 
the gain associated with the smaller geometry, and also as I recall some 
of the inputs to the 6-LUT are significantly faster than other inputs.

Am I complaining?  No, not really.  If I were to complain, it would be 
more about the new architecture making my existing library pretty much 
obsolete.

Marc Reinig wrote:

> We are currently planning on the V4 SX55, but really could use more speed, 
> pins, MACs and less power.  Looks like the speed increases slightly, 
> possibly more with the rearranged MAC; the power is down, that's good; will 
> there be an increase in the MACs and pins available?  Any indication of a 
> release date for samples?
> Marco
> ________________________
> Marc Reinig
> UCO/Lick Observatory
> Laboratory for Adaptive Optics
> 
> 

Marc,

The big win you'll see is that the V5 carry chain is fast enough to keep 
up with the DSP48E's, where in V4, the fabric carry chain speed is 
dismal compared to the speed of the DSP48's.  You'll have to get an NDA 
with Xilinx to get the details on planned V5SX devices.

Austin Lesea wrote:
> Kolja,
>
> Software is immediately available for the early access folks.
>
> The general release of Virtex-5 LX (minus the LX330) will be in the
> initial release of 8.2i which is about a month away.
>
> Austin
>
> Kolja Sulimma wrote:
>
> > Antti schrieb:
> >
> >
> >>1) Xilinx website says to the general public that 'start designing' NOW
> >>to my understanding it means that software support is available NOW, or
> >>is there is any other way to see it?
> >
> >
> > You can either download a text editor from the Xilinx Website or select
> > the "pencil and paper package" (5 weeks lead time) from the webshop to
> > start your HDL capture now.

Why do we change SW everytime a new device comes out? every 6 months?
Why can't have just a service pack...?

Unhappy sw user

Mr. Andraka (and others),

I am curious as to how you specify a single logic-layer in these
high-speed designs.  Do you explicitly specify the individual LUTs in
an HDL, or can you code at a higher level and synthesize down to
single-layer logic between flops?

Thank you,
Stephen Craven