requirements to select FPGA using LVDS

hi all,
wat all the basic requirements needed to be analysed before selecting a
FPGA chip for using high speed LVDS.
thanks in advance
praveen

1.  Can it support LVDS inputs/outputs. (many of the FPGA's do, both the low 
and high end )
2.  Does it have on chip terminating resistors for the receiver inputs. If 
not, you would have to put them on the PCB.
3.  You might be interested in the VCCIO voltages for the banks running the 
LVDS.  Some FPGA's want this voltage to be 2.5, which would necessitate 
another power source of some kind.
4.   I'm assuming by high-speed LVDS you mean a SERDES type interface.  The 
question then is, can the FPGA handle your speed?  For instance: if you have 
4 lanes with a x7 format running at 66MHz your serialized lanes will be 
running at 66MHz x 7 = 462Mbps.  Dealing with a SERDES interface requires a 
PLL (for instance) to generate the high-speed clock from the system clock 
(66MHz in my example).  The jitter spec on the FPGA becomes important 
because it will dictate how much skew the rest of the system (cable, board, 
etc) can tolerate.


<praveen.sethuram@gmail.com> wrote in message 
news:1147762433.451152.157990@i40g2000cwc.googlegroups.com...
> hi all,
> wat all the basic requirements needed to be analysed before selecting a
> FPGA chip for using high speed LVDS.
> thanks in advance
> praveen
> 

thanks Rob
i will certainly take this.