Hi everyone, For my design, which is implemented in Virtex-4 FX12 (speed grade -10) I need to get an adjustable (in operation) clock of frequency 30 to 66 MHz with the smallest possible increments. On the board I have 100MHz oscillator from which I tried to get 400 MHz (the higher the frequency the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX 4/1). From this DCM I also power the PPC at 200MHz (CLK2X). I coupled the 400MHz clock to clock divider using rising edge as a process reference and an integer counter. This configuration does NOT work. The first problem is the frequency - EDK can compile my design if I lower the frequency to 200MHz, which is unaceptable. The other problem is a structure of my clock divider - if I make a process with rising edge detection the clock divider can only be even (clock is always divided by a factor of two!). How to build a fast dual edge (DDR) clock divider in VHDL? Is there any other way to solve my problem? Help wanted, Guru
Virtex4 FX12 dynamic clock divider
Started by ●May 16, 2006
Reply by ●May 16, 20062006-05-16
The best way to create clocks with tiny increments is using Direct Digital Synthesis (DDS), a.k.a. phase accumulation. You just build a long accumulator, clock it from your 100 MHz (200 MHz would be better), and you can get at its MSB any frequency you want with any granularity you want (I built a circuit with 1 Hz resolution, but you can also get 1 millihertz.) The catch is jitter. You will create an unavoidable worst-case jitter of one clock period (10 ns or 5 ns in your case.) Reducing that jitter is very complicated. Peter Alfke, Xilinx Applications
Reply by ●May 16, 20062006-05-16
Guru schrieb:> For my design, which is implemented in Virtex-4 FX12 (speed grade -10) > I need to get an adjustable (in operation) clock of frequency 30 to 66 > MHz with the smallest possible increments. On the board I have 100MHzWhat is "smallest possible increment" If I spent a hell of stuff and money on it, I will have microhertz resolution with jitter down to a few picoseconds. Hey man, give us some numbers. Frequency resolution? Jitter?> oscillator from which I tried to get 400 MHz (the higher the frequency > the smaller the clock adjusting increments) using EDK 8.1's DCM (CLKFX > 4/1). From this DCM I also power the PPC at 200MHz (CLK2X). > I coupled the 400MHz clock to clock divider using rising edge as a > process reference and an integer counter. This configuration does NOT > work. The first problem is the frequency - EDK can compile my design if > I lower the frequency to 200MHz, which is unaceptable. The other > problem is a structure of my clock divider - if I make a process with > rising edge detection the clock divider can only be even (clock is > always divided by a factor of two!). > How to build a fast dual edge (DDR) clock divider in VHDL?Such a question from someone who calls himself Guru? ;-)> Is there any other way to solve my problem?There are many ways to skin a cat. One way is to have two counters, on counting on the rising edge, the other on the falling edge. Combining the two outputs in a clever fasion in a LUT can work. Or routing a signal to an output pin, make a connection to another pin back into the FPGA makes it possible to use the output DDR Flipflops. If you have a spare MGT, you can use it to make a real high frequncy DDS. Regards Falk
Reply by ●May 16, 20062006-05-16
Peter Alfke wrote:> The best way to create clocks with tiny increments is using Direct > Digital Synthesis (DDS), a.k.a. phase accumulation.Peter, Original poster mentioned that he was using V4. Can he use the dynamic reconfiguration feature of the DCM? If memory serves this allows for changing the M and D values. Regards, Erik. --- Erik Widding President Birger Engineering, Inc. (mail) 100 Boylston St #1070; Boston, MA 02116 (voice) 617.695.9233 (fax) 617.695.9234 (web) http://www.birger.com
Reply by ●May 16, 20062006-05-16
I think he can, but this gets us into the subject that Falk addressed, and I was too polite to mention: Be more specific! What is "smallest possible?" How much jitter is acceptable? If you can tolerate jitter, DDS is unbeatable. M/D still leaves big holes... Peter Alfke
Reply by ●May 17, 20062006-05-17
Here are some more details: The output clock is used for CMOS imaging sensor. The input clock can be 200MHz (CLK2X from DCM0) Desired clock increment is about 1 MHz. Maximum jitter not specified. 2 DCMs free for now. I think that DCM with dynamic FX ratios cannot produce such increments, because output frequency can only take fraction ratios according to input clock. I think DDS is the best solution for my problem. The open question is which frequency to take for input: 100, 200, 300 ..MHz? Thank you all, Guru
Reply by ●May 17, 20062006-05-17
it is possible to have virtual clock DDS you can calculate several phaseses per highest useable clock (200MHz) and use one output stage that combines the result, IO DDR primitive, you can so have DDS clock as if it would be 400MHz while still using max 200MHz real clock in the FPGA Antti
Reply by ●May 17, 20062006-05-17
Guru schrieb:> Here are some more details: > The output clock is used for CMOS imaging sensor. > The input clock can be 200MHz (CLK2X from DCM0) > Desired clock increment is about 1 MHz. > Maximum jitter not specified.Ahhh, now we move forward!> 2 DCMs free for now.> I think that DCM with dynamic FX ratios cannot produce such increments, > because > output frequency can only take fraction ratios according to input > clock. I think DDS is the best solution for my problem. The open > question is which frequency to take for input: 100, 200, 300 ..MHz?Lets look at the worst case. You want 66 MHz max. If we use some kind of 660 MHz master clock, we will have 1/10 UI jitter. Not too bad, not too good. I guess for the CMOS image sensor the jitter wont hurt, since it is read like a ram array, isnt it? So what you need is a multiphase DDS using lets say 4 accus. The MSBs must be parallel-serial converted using a x2 Clock and a DDR output stage. Been there, done that. Do a search in the FPGA FAQ, its explained there. Regards Falk
Reply by ●May 17, 20062006-05-17
Can IO DDR primitive output be used inside FPGA, because I need this clock also for several processes inside FPGA, or I have to route it to output I/O pin and then physically tie it to input I/O pin? By using DDR primitive I can theoretically get only 2.5ns jitter (+ logic delay) at 200 MHz input clock. Guru
Reply by ●May 17, 20062006-05-17
Guru schrieb:> Can IO DDR primitive output be used inside FPGA, because I need this > clock also for several processes inside FPGA, or I have to route it to > output I/O pin and then physically tie it to input I/O pin?Hmmm? Maybe you can do a trick. Define an bidirectional inout port, drive the output with the DDR FF and use the input as the (generated) clock. This may work.> By using DDR primitive I can theoretically get only 2.5ns jitter (+ > logic delay) at 200 MHz input clock.Logic delay doesnt matter for jitter, the delay is just a static phase shift. If you use a 300 MHz clock, you can go down to 1.6 ns. What device are you using? AFAIK Viertex-II etc. go up to 840 Mbit/s in DDR data transfer, Spartan-3 up to 622 Mbit/s. Regards Falk