SystemACE bootloader for PowerPC on Virtex4 FX

Hi,

I am looking for a small bootloader (small because I'd like it to be in
BRAM) that can load a PowerPC ELF file (possibly binary) from a CF card
connected via a SystemACE controller and run it. Any recommendations?

I've serached through the news group, and it seems like Antti wrote one
for MicroBlaze, although the link to xilinx.openchip.org no longer
seems to be valid. I've also had a look through xapp482.pdf, but I was
hoping someone had already implemented this before :)

Cheers,
Jon

hi, me Antti

yes I wrote some systemace loader that I tested on ML300 loooong time
ago
some derivate of that is still in use.
wasnt very good one, the FAT support was really really minimal :(

there should be no problems fitting into brams, but better look at the
dosfs
that is very small and support FAT pretty completly, changing the
sector read
for systemace should not be a problem

antti
I may be able to dig out some of my old code, buts its rather nasty

Jon Beniston wrote:
> Hi,
> 
> I am looking for a small bootloader (small because I'd like it to be in
> BRAM) that can load a PowerPC ELF file (possibly binary) from a CF card
> connected via a SystemACE controller and run it. Any recommendations?
> 

It is fairly straightforward to use xilfatfs (shipped with EDK) to load 
a file from the CF into memory and transfer control to the loaded 
program. Just use open/read file library calls.

/Siva

Hi Siva,

Yep, but a bog standard implementation (i.e. just using the standard
library code) is going to be 20kB+. I don't have that many block RAMs
to play with, so want to create something as small as possible.

Cheers,
Jon

Jon,

assuming that you are using System ACE CF to configure your Virtex-4 FX 
device you can load the boot code directly into the processor caches 
which gives you 16KB of instruction and 16KB of data space. That's 
enough for the bootloader you describe and you do not even need a single 
  BRAM.

- Peter


Jon Beniston wrote:
> Hi Siva,
> 
> Yep, but a bog standard implementation (i.e. just using the standard
> library code) is going to be 20kB+. I don't have that many block RAMs
> to play with, so want to create something as small as possible.
> 
> Cheers,
> Jon
> 

dosfs claims to be <4k but I havent checked it with mb-gcc or ppc-gcc
antti

"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag 
news:1147883675.279132.26480@y43g2000cwc.googlegroups.com...
> Hi Siva,
>
> Yep, but a bog standard implementation (i.e. just using the standard
> library code) is going to be 20kB+. I don't have that many block RAMs
> to play with, so want to create something as small as possible.
>
> Cheers,
> Jon
> 

Peter,

> assuming that you are using System ACE CF to configure your Virtex-4 FX

Yep.

> can load the boot code directly into the processor caches

Thanks sounds very interesting. Any pointers or app notes on how to do
this? (Sorry if I'm overlooking the obvious)

Cheers,
Jon

Hi Antti,

Do you have a link to this particular implementation? Is it open
source? (I have googled, but it seems there are lots of different
dosfs')

Cheers,
Jon

"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag 
news:1147890013.855465.165380@j33g2000cwa.googlegroups.com...
> Hi Antti,
>
> Do you have a link to this particular implementation? Is it open
> source? (I have googled, but it seems there are lots of different
> dosfs')
>
> Cheers,
> Jon
>
learn too google :)

its simple

google larwe dosfs
3 link

http://www.zws.com/products/dosfs/index.html

Antti 

"Jon Beniston" <jon@beniston.com> schrieb im Newsbeitrag 
news:1147889273.909649.117060@i40g2000cwc.googlegroups.com...
> Peter,
>
>> assuming that you are using System ACE CF to configure your Virtex-4 FX
>
> Yep.
>
>> can load the boot code directly into the processor caches
>
> Thanks sounds very interesting. Any pointers or app notes on how to do
> this? (Sorry if I'm overlooking the obvious)
>
> Cheers,
> Jon
>
xil appnotes and ref designs

pretty cool they use the USR ACCESS JTAG command to create virtual JTAG TAP 
master that then connects to the PPC JTAG tap and uses PPC ICE registers to 
load the caches. was pretty cool to see that implementation

look at the ultracontroller II, the thing is all there

antti