Hi, I've two development boards with me. 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG connector 2) Spartan 3E Starter Kit(XC3S500E) with a standard 6-pin JTAG interface and on-board digilent USB-JTAG interface. My question is that if I connect the two 6-pin JTAG connectors together like TDO<->TDI, TDI<->TDO,TCK<->TCK, TMS<->TMS and GND<->GND the VCCs are not connected. If this is done will the two boards show up together in the scan chain? The reason I want to do this is to debug the smaller board at usb speeds. Thanks, kishore.
JTAG chaining of two different Xilinx Spartan 3E boards
Started by ●May 20, 2006
Reply by ●May 20, 20062006-05-20
<firstname.lastname@example.org> wrote in message news:email@example.com...> Hi, > > I've two development boards with me. > 1) Spartan 3E Sample Pack(XC3S100E) with a standard 6-pin JTAG > connector > 2) Spartan 3E Starter Kit(XC3S500E) with a standard 6-pin JTAG > interface and on-board digilent USB-JTAG interface. > > My question is that if I connect the two 6-pin JTAG connectors > together like TDO<->TDI, TDI<->TDO,TCK<->TCK, TMS<->TMS and GND<->GND > the VCCs are not connected. If this is done will the two boards show up > together in the scan chain? > > The reason I want to do this is to debug the smaller board at usb > speeds. > > Thanks, > kishore. >I'm not sure if it will functionally work, but I would advise you to distribute and terminate TCK like any other fast rise/falltime clock. If you merely parallel (star or daisy-chain) TCK, without proper termination, you're asking for trouble. It's easiest just to use a clock buffer and source terminate each TCK separately. Bob
Reply by ●May 21, 20062006-05-21
Keep the cabling from the USB/JTAG adapter short, and in particular, keep the stub lengths for TCK and TMS short and it should work. I've built/used debug rigs that used JTAG (albeit for Pentium processors, not FPGA's), and it's more robust than you would imagine. I've seen JTAG work reliably with clock stubs nearly 6" long made out of standard 22 guage wire using regular header posts. (like the ones on the sample kit board) The only caveat is that I measured the wires such that the lines were all very closely matched. More to the point, you aren't going to harm anything so long as you don't connect the two independent VCC lines together, so give it a go. I don't know if Xilinx supports it, but Altera tools will let you run a verification loop through the chain - if it passes, you are fairly assured the chain is good. If it doesn't work by just keeping the cabling to a minimum, you can always try inserting a clock buffer/driver and using independent outputs for each board - but keep in mind a normal buffer will add skew to the clock. Try to use a clock driver that uses a built-in PLL or DLL to negate the skew. Linear and IDT both have parts that are "zero-skew". Same thing applies, though - keep the cabling short. I suspect that you will find an appropriate harness to be adequate, though. Please post your findings. I'm planning on doing something very similar, as I recently received a freebie S3E sample pack, and I'm waiting on my freebie Coolrunner CPLD board.