Verilog vs VHDL

Hi,

     I know this has been brought up many times in various groups but
here is my view on them and I would really appreciate some
clarification. I started working on FPGA design and stuff some 3 months
back or so. All the time I was switching back and forth between verilog
and VHDL for various projects. I personally feel that one can be very
productive as in time with Verilog? I only use VHDL if there is no
choice but I am not aganist VHDL or anything.

     After some searching on google and various usenet groups I came
across many arguments regarding Verilog vs VHDL  summarising either as
"use the right the tool for the right job" or "leading to language
wars". I am open-minded and I am biased to the former at the same time
a bit biased to verilog :) I just wanted to know some things.

-> Are there things that VHDL does better than verilog or vice-versa
-> What is the most widely used language in the industry i.e. FPGA and
ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
VHDL?

   All kinds of thoughts, experiences and constructive criticisms will
be helpful.

cheers,
kishore.

-> Are there things that VHDL does better than verilog or vice-versa

Enumerated data types.

> What is the most widely used language in the industry i.e. FPGA and ASIC designs

Probably 50-50.

Cheers,
Jon

On 23 May 2006 14:50:44 -0700, "Jon Beniston" <jon@beniston.com>
wrote:

>-> Are there things that VHDL does better than verilog or vice-versa
>
>Enumerated data types.
>
>> What is the most widely used language in the industry i.e. FPGA and ASIC designs
>
>Probably 50-50.

Here is my very simple research: go to monster.com and search for
verilog and vhdl keywords. Here are the results:

			verilog (%) 		vhdl (%)
overall 			387 (55)		320 (45)
100 miles around 	104 (78)		30 (22)
zipcode 94087

94087 is zipcode of Sunnyvale, CA.

It's usually said VHDL is more popular in Europe.

Cheers,
Jon

Kishore wrote:
> -> What is the most widely used language in the industry i.e. FPGA and
> ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
> VHDL?

Most Xilinx IP cores are delivered as VHDL for parameterization reasons, but
we release a lot of Verilog code as well.   Invariably when we release
and application note with only one language we get an immediate request
for the other.

Personally I prefer Verilog (I find it quicker to code and debug in than
VHDL), but I've written just about as much VHDL.

Ed McGettigan
--
Xilinx Inc.

Kishore wrote:
> I personally feel that one can be very
> productive as in time with Verilog? 

If that is a conviction rather than a question
why not get back to writing code?

> -> Are there things that VHDL does better than verilog 

variables

> -> What is the most widely used language in the industry i.e. FPGA and
> ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
> VHDL?

totally?

I've been trolled.
I should really get back to writing code . . .

          -- Mike Treseler

On Tue, 23 May 2006 22:04:23 +0000, mk wrote:

> Here is my very simple research: go to monster.com and search for
> verilog and vhdl keywords. Here are the results:
> 
> 			verilog (%) 		vhdl (%)
> overall 			387 (55)		320 (45)
> 100 miles around 	104 (78)		30 (22)
> zipcode 94087
> 
> 94087 is zipcode of Sunnyvale, CA.
 
I did this for a smattering of different states a month ago and came up
with 60% Verilog vs 40% VHDL.  We're pretty close.

The OP should google "verilog vs vhdl" for a lot of info.


    ~Dave~

Kishore wrote:
> Hi,
>
>      I know this has been brought up many times in various groups but
> here is my view on them and I would really appreciate some
> clarification. I started working on FPGA design and stuff some 3 months
> back or so. All the time I was switching back and forth between verilog
> and VHDL for various projects. I personally feel that one can be very
> productive as in time with Verilog? I only use VHDL if there is no
> choice but I am not aganist VHDL or anything.
>
>      After some searching on google and various usenet groups I came
> across many arguments regarding Verilog vs VHDL  summarising either as
> "use the right the tool for the right job" or "leading to language
> wars". I am open-minded and I am biased to the former at the same time
> a bit biased to verilog :) I just wanted to know some things.
>
> -> Are there things that VHDL does better than verilog or vice-versa
> -> What is the most widely used language in the industry i.e. FPGA and
> ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
> VHDL?
>
>    All kinds of thoughts, experiences and constructive criticisms will
> be helpful.
>
> cheers,
> kishore.

VHDL was often said to be used more in Europe, DOD, and in the schools
and now perhaps in FPGAs too.

I am always surprised to hear about Verilog use in schools or outside
the US but I am biased to Verilog mostly because I use only a tiny
fraction of the language anyway and come from the ASIC background.

At one time Verilog had a bulls eye mark on it by the EDA industry. The
US ASIC guys had chosen Verilog  and liked it enough because it had
cell library support and could be mixed with C tools via the PLI.
Verilog had been proprietary but when taken over by Cadence, it was
released as an open standard. Phil Moorby had gone to Cadence along
with his language and for awhile the entire EDA industry was going
against Verilog and pronounced it as dead. Even Cadence people could
only say Verilog under their breadth as politically incorrect. The
customers eventually won out and atleast in the US Verilog still
dominates in ASICs. It also helped that Synopsys took on Verilog for
synthesis and pushed it forward no end. VHDl though came in right
behind.

Trouble is as some will point out, ASIC starts are dying, FPGA designs
are growing and the nature of design in both of these is quite
different, huge teams v tiny teams, high risk v low risk.

In olden times, Verilog had alot more useablity at a low level for gate
and device level modeling, which nobody really does anymore since
synthesis took over.

VHDL always had advantages in higher level modelling. I think they
overlapped by 70% but used different language constructs to say the
same thing, Verilog generally used about half the key strokes.

Nowadays in the ASIC world Verilog is getting replaced by SuperLog now
known as SystemVerilog which borrowed/stole several of VHDLs language
features. I do wish Verilog could abandon some of its old features
though and get light again.

Anyway the wars are really over, both the standards groups merged into
one camp,. Officially  both languages are merging in a way that neither
could have predicted. Most EDA tools have 2 parsers in front end and a
common language internal engine. Its more hassle to support this but it
will go on for some time.

John Jakson
transputer guy

My work is usually split 50/50 between the two.  When asked which I
prefer, I usually reply "the other one".  Which ever one I'm currently
using, I always wish I was using the other.

In today's designs, you're (almost) always integrating IP from various
vendors, and odds are   you'll be integrating modules written in both
languages.

Learn both.

> -> Are there things that VHDL does better than verilog or vice-versa

Yes, yes

> -> What is the most widely used language in the industry i.e. FPGA and
> ASIC designs. I think VHDL is the dominant one as Xilinx totally uses
> VHDL?

both plus other.

I see Verliog getting more and more replaced by SystemVerilog.
WIth SV you enable Verilog designer to do everything you could do with
VHDL including the most disadvantage of VHDL: writing bad code.

A more detailed view is availabel under
http://groups.google.com/groups?as_oq=vhdl+verilog
or in several other discussions around the web.
On a first glance you gain abstraction levels by walking along
Verilog -> VHDL -> SystemVerilog -> SystemC
Each gain in abstraction level costs you more effort to ensure your
code is not too abstract for your task. 

bye Thomas