Forums

State Machines....

Started by stan November 19, 2003
hi ... I have a question for the experts , I am doing a post mortem of
my last project , it was a communication processor that was basicly a
lot of dataflow paths controlled by several rather complex state
machines ( 100-200 states ) ,  I did the design by thinking out the
control and drawing the state diagrams and then coding them into VHDL
for Quartus and into a Stratix .. it worked , after handing over the
design to the test department they loaded a board and signed off on
the design within a week. My fellow engineers were rather impressed
since they knew how complex the control was.

The downside here was the state machines became complex and took quite
a while to figure out ... then transcibing them into VHDL and also
drawing a pretty state chart for documenting the design took a while.
Yes I know some say start right with typing VHDL but I find that hard
to comceptualize.  Since this is a small company big $$ tools are out
of the question.

So my question ... are there tools out there that can make this
process faster ?  like drawing the state charts on the screen and
outputing VHDL ?  or other suggestions ???  again if these are $5-10K
tools I won't be getting them in this company so shareware or <$1K
tools are preferred even if they lack in some areas.

The bigger downside here is that since the state machines took longer
than I expected ( I scheduled 3 weeks of design, project took 6 weeks
)  my manager has warned me to find another job ( fat chance ) as he
has handed in a review requesting a 20% pay cut ... but my real
question is about the tools so I may do better next time

thanks for any constructive feedback , stan
> The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time
I think you do need to find another job with a better manager! An error in scheduling made by an engineer doesn't deserve a pay cut. If anyone deserves a pay cut, it's a manager who didn't know a basic management rule: take an engineer's estimate, multiply it by 2 and then use the next available unit :) If he knew the rule he would celebrate the work finished way faster than expected! /Mikhail
"stan" <stanandsue2000@yahooREMOVE.com> wrote in message
news:3fbb8795.3574357@news.compuserve.com...

[...]
> lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question.
I don't know of any really free tools, but isn't there still a state chart editor in the Xilinx tools? However... Obviously I don't know the insides of your application, but 100-200 states sounds like a real behemoth. Isn't there some way you could partition it and make it hierarchical? Alternatively, it might make sense to think in terms of a microcoded solution - a custom state sequencer engine, and a little ROM containing the sequence information. Way back in the bad old days of the late 80s there was a nifty little thing from AMD called the 29PL141 that would probably have helped. One of my "must do one of these fine days" jobs is to write an HDL implementation of that - I still have all the original AMD docs on one of my bookshelves at home. Anyhow, here's my main point: state diagrams are supposed to be clear and self-evident; if they're too big to be clear and self-evident, then perhaps they are the wrong tool for the problem at hand. Similarly, if you have a state diagram of modest size, converting it into VHDL or Verilog is pretty much a no-brainer. Now, if you managed to get this leviathan to work first time, you obviously know what you're doing and I'm sure you thought of these things for yourself. So, can you offer a clue about *why* your state machines needed to be so huge? and *why* you couldn't make them hierarchical? It would be very interesting to hear your experiences. Cheers -- Jonathan Bromley, Consultant DOULOS - Developing Design Know-how VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com Fax: +44 (0)1425 471573 Web: http://www.doulos.com The contents of this message may contain personal views which are not the views of Doulos Ltd., unless specifically stated.
On Wed, 19 Nov 2003 15:33:46 GMT, stanandsue2000@yahooREMOVE.com
(stan) wrote:

<<good state machine story snipped>>

I've tried Statecad, which I believe is the progenitor of today's
Xilinx state machine graphical entry tool.  Rather than saving me
time, the tool made me guess as to just what I'd have to do to get
what I wanted in hardware.  Maybe if you spent more time at it than I
did it'd be worth it, but I find it easier to design in Verilog.  The
fewer tools between you and the hardware, the better.

I'd have to agree with others who said that you probably should have
given more thought to decomposing your FSMs into smaller ones.  This
is more art than science, and I don't know of any good references that
explain how to do this; most people learn from someone else, or from
experiences such as yours, after which they vow, "No more huge state
machines."

You're to be congratulated on doing a thorough enough job on design
that debug went smoothly.  Perhaps you deserve a better manager.

Bob Perlman
Cambrian Design Works
stan wrote:
> hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. > > So my question ... are there tools out there that can make this > process faster ? like drawing the state charts on the screen and > outputing VHDL ? or other suggestions ??? again if these are $5-10K > tools I won't be getting them in this company so shareware or <$1K > tools are preferred even if they lack in some areas. > > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time > > thanks for any constructive feedback , stan
My first rules, when describing a complex fsm, is to try to minimize the number of signal generated by one fsm, and to write many concurrent fsm. One process for one generated signal, and multiply the process. Normal fsm construction can have two or three process. Then for one fsm do not generate more than 3-5 signals (or vector). If you have to generate 100 signals, I will write 20 concurrent fsm. Laurent www.amontec.com
stan wrote:
> hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. > > So my question ... are there tools out there that can make this > process faster ? like drawing the state charts on the screen and > outputing VHDL ? or other suggestions ??? again if these are $5-10K > tools I won't be getting them in this company so shareware or <$1K > tools are preferred even if they lack in some areas. > > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time > > thanks for any constructive feedback , stan
My first rules, when describing a complex fsm, is to try to minimize the number of signal generated by one fsm, and to write many concurrent fsm. One process for one generated signal, and multiply the process. Normal fsm construction can have two or three process. Then for one fsm do not generate more than 3-5 signals (or vector). If you have to generate 100 signals, I will write 20 concurrent fsm. Laurent www.amontec.com
Stan -

I agree with Jonathan that 200 states is nuts. Very error prone and
probably very difficult to maintain/modify. Were you parsing the
incoming data stream and making state decisions based on that? If so, a
programmable communications processor or an embedded processor (like
Nios for Altera) is a much better and more flexible choice. Some tasks
just aren't meant to be done in hardware, and parsing data streams is
one of them.

Nice reward for delivering a working design. I hope you find a way to
exit that situation.

Robert

"stan" <stanandsue2000@yahooREMOVE.com> wrote in message
news:3fbb8795.3574357@news.compuserve.com...
> hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , I did the design by thinking out the > control and drawing the state diagrams and then coding them into VHDL > for Quartus and into a Stratix .. it worked , after handing over the > design to the test department they loaded a board and signed off on > the design within a week. My fellow engineers were rather impressed > since they knew how complex the control was. > > The downside here was the state machines became complex and took quite > a while to figure out ... then transcibing them into VHDL and also > drawing a pretty state chart for documenting the design took a while. > Yes I know some say start right with typing VHDL but I find that hard > to comceptualize. Since this is a small company big $$ tools are out > of the question. > > So my question ... are there tools out there that can make this > process faster ? like drawing the state charts on the screen and > outputing VHDL ? or other suggestions ??? again if these are $5-10K > tools I won't be getting them in this company so shareware or <$1K > tools are preferred even if they lack in some areas. > > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job ( fat chance ) as he > has handed in a review requesting a 20% pay cut ... but my real > question is about the tools so I may do better next time > > thanks for any constructive feedback , stan
There is an April 2001 TechXclusives "Using leftover multipliers and
BlockRAMs" that describes a surprisingly simple structure for a state
machine with up to 256 states. I never got any feedback on this idea.
There is no software tool, but it's pretty straightforward, and "pencil
and paper" might suffice...
http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp

Peter Alfke, Xilinx Applications 
=============================
Robert Sefton wrote:
> > Stan - > > I agree with Jonathan that 200 states is nuts. Very error prone and > probably very difficult to maintain/modify. Were you parsing the > incoming data stream and making state decisions based on that? If so, a > programmable communications processor or an embedded processor (like > Nios for Altera) is a much better and more flexible choice. Some tasks > just aren't meant to be done in hardware, and parsing data streams is > one of them. > > Nice reward for delivering a working design. I hope you find a way to > exit that situation. > > Robert > > "stan" <stanandsue2000@yahooREMOVE.com> wrote in message > news:3fbb8795.3574357@news.compuserve.com... > > hi ... I have a question for the experts , I am doing a post mortem of > > my last project , it was a communication processor that was basicly a > > lot of dataflow paths controlled by several rather complex state > > machines ( 100-200 states ) , I did the design by thinking out the > > control and drawing the state diagrams and then coding them into VHDL > > for Quartus and into a Stratix .. it worked , after handing over the > > design to the test department they loaded a board and signed off on > > the design within a week. My fellow engineers were rather impressed > > since they knew how complex the control was. > > > > The downside here was the state machines became complex and took quite > > a while to figure out ... then transcibing them into VHDL and also > > drawing a pretty state chart for documenting the design took a while. > > Yes I know some say start right with typing VHDL but I find that hard > > to comceptualize. Since this is a small company big $$ tools are out > > of the question. > > > > So my question ... are there tools out there that can make this > > process faster ? like drawing the state charts on the screen and > > outputing VHDL ? or other suggestions ??? again if these are $5-10K > > tools I won't be getting them in this company so shareware or <$1K > > tools are preferred even if they lack in some areas. > > > > The bigger downside here is that since the state machines took longer > > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > > ) my manager has warned me to find another job ( fat chance ) as he > > has handed in a review requesting a 20% pay cut ... but my real > > question is about the tools so I may do better next time > > > > thanks for any constructive feedback , stan
"Peter Alfke" <peter@xilinx.com> ha scritto nel messaggio
news:3FBBB033.E8A6616A@xilinx.com...

> There is an April 2001 TechXclusives "Using leftover multipliers and > BlockRAMs" that describes a surprisingly simple structure for a state > machine with up to 256 states. I never got any feedback on this idea. > There is no software tool, but it's pretty straightforward, and "pencil > and paper" might suffice... > http://support.xilinx.com/xlnx/xweb/xil_tx_home.jsp
Just read the article... I like the idea, I'll try to remember the trick next design. Makes medium/big fsm simplicity itself: no routing issues, etc.. very clever. But... too much work for translating to numeric "init" format... Why don't you try to "whisper" a bit at the ears of ISE StateCad mantainers ? Maybe outputting INIT tables from a StateCad graph could boost the use of this particular trick.
stan wrote:
> hi ... I have a question for the experts , I am doing a post mortem of > my last project , it was a communication processor that was basicly a > lot of dataflow paths controlled by several rather complex state > machines ( 100-200 states ) , >
Some hardware objects are not efficiently described as a state machine. For example, an 8 bit shift register could be described using a single variable assignment or as a case of 256 variable states. Complex sequential logic is easiest for me to describe using clocked processes with lots of local variables. The state machine model is a clocked process with a single enumerated local variable or signal. With a state editor as your design entry, this is all you can do. With synthesis tools, you can have many local variables of many types in a single clocked process. You might have a local counter register and a shift register, etc. One page of clear code replaces pages of circles and arrows. > The bigger downside here is that since the state machines took longer > than I expected ( I scheduled 3 weeks of design, project took 6 weeks > ) my manager has warned me to find another job I expect that he could not really find anyone faster. Keep honing your skills, and politely ignore the "schedule as whip" tactic. -- Mike Treseler