Forums

Quartus II Node Finder

Started by Vazquez November 20, 2003
Dear Sir or Madame,

attached you see a test project file.

After compiling the design I open the Node Finder.
I use the following filter : Design entry (all names)

Why is the signal "vector_out" (entity test.vhd)
(which is  concurrently assigned by the registered signal
"l_vector")   and the corresponding port map signal (toplevel entity)
"l_vector_out" shown to be combinatorial although they are
registers?
A change of the filter type does not change the result.

Why do these signals not appear as registers in the NodeFinder?

Thank you very much.

Kind regards

A. Vazquez

toplevel file
------------------------------------------------------
------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

entity test_hierarch is
port( clk_in   : in  std_logic;
      reset_in : in  std_logic;
      invec    : in  std_logic_vector(3 downto 0);
      set      : in  std_logic_vector(3 downto 0);
      show     : out std_logic
    );
end test_hierarch;


architecture rtl of test_hierarch is

   component test is
             port( clk        : in  std_logic;
                   reset      : in  std_logic;
                   indelay    : in  std_logic_vector(3 downto 0);
                   vector_out : out std_logic_vector(3 downto 0)
                  );
   end component;

-- local signals
signal l_vector_out : std_logic_vector(3 downto 0);

begin

i1 : test
port map ( clk        => clk_in,
           reset      => reset_in,
           indelay    => invec,
           vector_out => l_vector_out
          );

 process(reset_in, clk_in)
 begin
    if reset_in='1' then
       show <= '0';
    elsif clk_in='1' and clk_in'event then
       if ( (l_vector_out = "0001") and (set="1111") ) then
          show <= '1';
       end if;
    end if;
 end process;
end rtl;
----------------------------------------------------
----------------------------------------------------



component file
-----------------------------------------------------
-----------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;


entity test is
port( clk        : in  std_logic;
      reset      : in  std_logic;
      indelay    : in  std_logic_vector(3 downto 0);
      vector_out : out std_logic_vector(3 downto 0)
    );
end test;

architecture behavior of test is

signal l_vector : std_logic_vector(3 downto 0);

begin

-- concurrent statement
vector_out <= l_vector;
--

 process(clk, reset)
 begin
   if reset='1' then
      l_vector <= (others => '0');

   elsif clk='1' and clk'event then
      l_vector <= indelay;
   end if;
 end process;

end behavior;

-----------------------------------------------
-----------------------------------------------
andres.vazquez@gmx.de (Vazquez) wrote in message news:<eee19a7a.0311200628.263b82c9@posting.google.com>...
> Dear Sir or Madame, > > attached you see a test project file. > > After compiling the design I open the Node Finder. > I use the following filter : Design entry (all names) > > Why is the signal "vector_out" (entity test.vhd) > (which is concurrently assigned by the registered signal > "l_vector") and the corresponding port map signal (toplevel entity) > "l_vector_out" shown to be combinatorial although they are > registers? > A change of the filter type does not change the result. > > Why do these signals not appear as registers in the NodeFinder? > > Thank you very much. >
> Kind regards > > A. Vazquez > > toplevel file > ------------------------------------------------------ > ------------------------------------------------------ > > library ieee; > > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > > entity test_hierarch is > port( clk_in : in std_logic; > reset_in : in std_logic; > invec : in std_logic_vector(3 downto 0); > set : in std_logic_vector(3 downto 0); > show : out std_logic > ); > end test_hierarch; > > > architecture rtl of test_hierarch is > > component test is > port( clk : in std_logic; > reset : in std_logic; > indelay : in std_logic_vector(3 downto 0); > vector_out : out std_logic_vector(3 downto 0) > ); > end component; > > -- local signals > signal l_vector_out : std_logic_vector(3 downto 0); > > begin > > i1 : test > port map ( clk => clk_in, > reset => reset_in, > indelay => invec, > vector_out => l_vector_out > ); > > process(reset_in, clk_in) > begin > if reset_in='1' then > show <= '0'; > elsif clk_in='1' and clk_in'event then > if ( (l_vector_out = "0001") and (set="1111") ) then > show <= '1'; > end if; > end if; > end process; > end rtl; > ---------------------------------------------------- > ---------------------------------------------------- > > > > component file > ----------------------------------------------------- > ----------------------------------------------------- > library ieee; > use ieee.std_logic_1164.all; > use ieee.std_logic_arith.all; > > > entity test is > port( clk : in std_logic; > reset : in std_logic; > indelay : in std_logic_vector(3 downto 0); > vector_out : out std_logic_vector(3 downto 0) > ); > end test; > > architecture behavior of test is > > signal l_vector : std_logic_vector(3 downto 0); > > begin > > -- concurrent statement > vector_out <= l_vector; > -- > > process(clk, reset) > begin > if reset='1' then > l_vector <= (others => '0'); > > elsif clk='1' and clk'event then > l_vector <= indelay; > end if; > end process; > > end behavior; > > ----------------------------------------------- > -----------------------------------------------
"vector_out" and "l_vector_out" are wires that are connected to the register "l_vector". Quartus considers wires to be combinational entities, even if they are electrically connected to the output of a register. Subroto Datta Altera Corp.