Rumor Control:: Will Quartus phase out supporting AHDL?

Hello, I posted this question a while back but I'm hearing the rumor
again from people attending Altera's Quartus workshops. The rumor is
that Altera may eventually phase out their support of AHDL in their
Quartus development software. Does anyone know what's in the future for
AHDL?

Thanks,
joe

jjlindula@hotmail.com wrote:
> Hello, I posted this question a while back but I'm hearing the rumor
> again from people attending Altera's Quartus workshops. The rumor is
> that Altera may eventually phase out their support of AHDL in their
> Quartus development software. Does anyone know what's in the future for
> AHDL?
>
> Thanks,
> joe

Hi Joe,

  AHDL support will be there in Quartus for a long long time.The AHDL
language, is fully maintained and supported for reasons of backwards
compatibility. There are lots of legacy Max+Plus II designs which
customers are migrating to Quartus for use in both existing and new
projects. We are sensitive to our customers needs and will not do
anything to jeopardize their productivity.

Hope this helps,
Subroto Datta
Altera Corp.

jjlindula@hotmail.com wrote:

> Hello, I posted this question a while back but I'm hearing the rumor
> again from people attending Altera's Quartus workshops. The rumor is
> that Altera may eventually phase out their support of AHDL in their
> Quartus development software. Does anyone know what's in the future for
> AHDL?

  I can see that they would move AHDL to "maintenance mode", but I doubt
they would kill it entirely.

  Altera took some trouble to keep the MAX +II interface option, and
CPLDs must still be a sizeable chunk of their business.

  I liked what Xilinx did with ABEL : that now generates VHDL output 
(IIRC), and so can hook into all the back end tools, whilst at the
same time, preserve customers code base.
  In this form, ABEL is a valid choice for new designs ( esp in the
CPLD arena ).

  Altera could do the same, with their AHDL (or may have already).

  Someone at Altera may clarify this ?

-jg

I find it interesting that Xilinx webpack has tools to convert AHDL to
VHDL, but Altera does not!  Of course, the copyright notice included in
the generated code restricts its use to Xilinx products.

Andy


Jim Granville wrote:
> jjlindula@hotmail.com wrote:
>
> > Hello, I posted this question a while back but I'm hearing the rumor
> > again from people attending Altera's Quartus workshops. The rumor is
> > that Altera may eventually phase out their support of AHDL in their
> > Quartus development software. Does anyone know what's in the future for
> > AHDL?
>
>   I can see that they would move AHDL to "maintenance mode", but I doubt
> they would kill it entirely.
>
>   Altera took some trouble to keep the MAX +II interface option, and
> CPLDs must still be a sizeable chunk of their business.
>
>   I liked what Xilinx did with ABEL : that now generates VHDL output
> (IIRC), and so can hook into all the back end tools, whilst at the
> same time, preserve customers code base.
>   In this form, ABEL is a valid choice for new designs ( esp in the
> CPLD arena ).
>
>   Altera could do the same, with their AHDL (or may have already).
> 
>   Someone at Altera may clarify this ?
> 
> -jg

Andy wrote:
> I find it interesting that Xilinx webpack has tools to convert AHDL to
> VHDL, but Altera does not! 

Yes. In fact Quartus synthesis still maps
a few VHDL code templates to
.tdf (AHDL) blocks.

Still some reptile brain inside :)

              -- Mike Treseler

Andy wrote:
> I find it interesting that Xilinx webpack has tools to convert AHDL to
> VHDL, but Altera does not!  Of course, the copyright notice included in
> the generated code restricts its use to Xilinx products.

  Given Subroto's reply, why would Altera need to do this ?
AHDL works fine, and is supported.

  Xilinx, on the other hand, have to oil the pathways for
Altera users, so they have to offer something...

-jg

Subroto Datta napisa�/a:
>   AHDL support will be there in Quartus for a long long time.The AHDL
> language, is fully maintained and supported for reasons of backwards
> compatibility. There are lots of legacy Max+Plus II designs which
> customers are migrating to Quartus for use in both existing and new
> projects. We are sensitive to our customers needs and will not do
> anything to jeopardize their productivity.

Is backward compatibility the only reason why Altera keeps AHDL in 
Quartus? Which languages Altera suggests to use in new projects?

czerstwy

> 
> Is backward compatibility the only reason why Altera keeps AHDL in 
> Quartus? Which languages Altera suggests to use in new projects?
> 
> czerstwy

You would never want to start a new project in an obsolete language like
AHDL or ABEL. Verilog and VHDL are the only reasonable choices for new
designs, personally I use Verilog but I don't want to start a religious
war so lets just say both of those languages are industry standards and
that code written in either can be easily ported to anybody's FPGA or ASIC.

I would suggest VHDL as a replacement for AHDL as the two are similar.
Simon

"Josh Rosen" <bjrosen@polybusPleaseDontSPAMme.com> wrote in message
news:pan.2006.06.09.19.35.20.613577@polybusPleaseDontSPAMme.com...
> >
> > Is backward compatibility the only reason why Altera keeps AHDL in
> > Quartus? Which languages Altera suggests to use in new projects?
> >
> > czerstwy
>
> You would never want to start a new project in an obsolete language like
> AHDL or ABEL. Verilog and VHDL are the only reasonable choices for new
> designs, personally I use Verilog but I don't want to start a religious
> war so lets just say both of those languages are industry standards and
> that code written in either can be easily ported to anybody's FPGA or
ASIC.
>
>
>

Hello, both VHDL and Verilog are well established standards that have been 
widely adopted by the engineering community. Excellent behavioral simulators 
are available for both of the languages. Therefore it would be prgamatic to 
use Verilog and VHDL for new projects. AHDL is simple to use but a lot of 
what can be done in AHDL can be accomplished with Verilog and VHDL. As 
language parsing and synthesis are two separate processing steps all three 
languages benefit from the improvements that are made to the Quartus core 
logic synthesis and technology mapping algorithms. Therefore you will be 
able to achieve equivalent Quality of Results with all three languages.

- Subroto Datta
Altera Corp.

"czerstwy" <czebaka@o2.pl> wrote in message 
news:e6cc9t$2tg$1@news.onet.pl...
> Subroto Datta napisa&#4294967295;/a:
>>   AHDL support will be there in Quartus for a long long time.The AHDL
>> language, is fully maintained and supported for reasons of backwards
>> compatibility. There are lots of legacy Max+Plus II designs which
>> customers are migrating to Quartus for use in both existing and new
>> projects. We are sensitive to our customers needs and will not do
>> anything to jeopardize their productivity.
>
> Is backward compatibility the only reason why Altera keeps AHDL in 
> Quartus? Which languages Altera suggests to use in new projects?
>
> czerstwy