Current from FPGA pins to ADC

I want to use a Spartan II chip to drive two ADCs. The ADC spec says
that the input current on the SCLK pin is +/-0.5uA max and 10nA
typically. Similary the input current on the CS pin is 10nA typically.
The absolute maximum ratings for the same ADC state that the maximum
input current to any pins (except supplies) is +/-10mA. I'm using the
LVTTL standard and can only specify the drive current to a minimum of
2mA. Will I be doing the ADCs potential damage if I specify 2mA to
drive the SCLK and CS pins? 

Thanks,
Mees

Mees, don't worry about the currents, just make sure that the voltage
ramges for FPGA and ADC are compatible.
Peter Alfke, Xilinx
=======
m_oylulan@hotmail.com wrote:
> I want to use a Spartan II chip to drive two ADCs. The ADC spec says
> that the input current on the SCLK pin is +/-0.5uA max and 10nA
> typically. Similary the input current on the CS pin is 10nA typically.
> The absolute maximum ratings for the same ADC state that the maximum
> input current to any pins (except supplies) is +/-10mA. I'm using the
> LVTTL standard and can only specify the drive current to a minimum of
> 2mA. Will I be doing the ADCs potential damage if I specify 2mA to
> drive the SCLK and CS pins? 
> 
> Thanks,
> Mees

Mees,

Current only makes sense when there is a path for it. In your case the
current will go through the input impedance of your ADC. The extremely small
current value given in its datasheet (10nA typically) is essentially leakage
current typical for high-impedance CMOS inputs. Thus, since the input
impedance is high you will never see anything close to absolute limits of
the chip pretty much regardless of the drive strength you choose. The drive
strength only tells you how much current a driver CAN drive while keeping
the output voltage range in spec. If there is no load, there is current.


/Mikhail





<m_oylulan@hotmail.com> wrote in message
news:1149870335.699238.81850@f6g2000cwb.googlegroups.com...
> I want to use a Spartan II chip to drive two ADCs. The ADC spec says
> that the input current on the SCLK pin is +/-0.5uA max and 10nA
> typically. Similary the input current on the CS pin is 10nA typically.
> The absolute maximum ratings for the same ADC state that the maximum
> input current to any pins (except supplies) is +/-10mA. I'm using the
> LVTTL standard and can only specify the drive current to a minimum of
> 2mA. Will I be doing the ADCs potential damage if I specify 2mA to
> drive the SCLK and CS pins?
>
> Thanks,
> Mees
>

Peter Alfke wrote:
> Mees, don't worry about the currents, just make sure that the voltage
> ramges for FPGA and ADC are compatible.
> Peter Alfke, Xilinx
> =======
> m_oylulan@hotmail.com wrote:
> > I want to use a Spartan II chip to drive two ADCs. The ADC spec says
> > that the input current on the SCLK pin is +/-0.5uA max and 10nA
> > typically. Similary the input current on the CS pin is 10nA typically.
> > The absolute maximum ratings for the same ADC state that the maximum
> > input current to any pins (except supplies) is +/-10mA. I'm using the
> > LVTTL standard and can only specify the drive current to a minimum of
> > 2mA. Will I be doing the ADCs potential damage if I specify 2mA to
> > drive the SCLK and CS pins?
> >
> > Thanks,
> > Mees

Thanks for the responses.
I am not sure if anyone is still reading this, but I've tested
the ADC with worrying results. When I apply a sine wave to the input
of the ADC with no SCLK or CS signal from FPGA, I can clearly
see the sinewave on an oscilloscope. When I then use the FPGA
to drive the CS and SCLK pins, the pure sine wave input to the
ADC is no longer visible on the scope. What I see instead is what
appears to be a bouncing noisy signal with sharp peaks and troughs.
Similarly the ADC output consists of sharp periodic spikes. My SLCK
and CS signals don't look very clean on the scope. How can I improve
the quality of these if I need to drive the ADC from the FPGA? What
else should I consider to resolve this problem?

Thanks,

Mees

m_oylulan@hotmail.com schrieb:

> Thanks for the responses.
> I am not sure if anyone is still reading this, but I've tested
> the ADC with worrying results. When I apply a sine wave to the input
> of the ADC with no SCLK or CS signal from FPGA, I can clearly
> see the sinewave on an oscilloscope. When I then use the FPGA

I guess you are probing the ADC input. So far so good.

> to drive the CS and SCLK pins, the pure sine wave input to the
> ADC is no longer visible on the scope. What I see instead is what
> appears to be a bouncing noisy signal with sharp peaks and troughs.

Could may many problems. Is your probe connected properly? Properly 
ground connection? Is the layout done properly (ADC require special care 
to avoid crossing of digital and analog currents.)

> Similarly the ADC output consists of sharp periodic spikes. My SLCK
> and CS signals don't look very clean on the scope. How can I improve

Looks like bad probing. Probe properly.

> the quality of these if I need to drive the ADC from the FPGA? What
> else should I consider to resolve this problem?

Apply basic engineering. Proper probing, layout. try to use slow FPGA 
output with low drive current (4mA should do if clock frequencies are 
below say 50 MHz)

Regards
Falk

>I am not sure if anyone is still reading this, but I've tested
>the ADC with worrying results. When I apply a sine wave to the input
>of the ADC with no SCLK or CS signal from FPGA, I can clearly
>see the sinewave on an oscilloscope. When I then use the FPGA
>to drive the CS and SCLK pins, the pure sine wave input to the
>ADC is no longer visible on the scope. What I see instead is what
>appears to be a bouncing noisy signal with sharp peaks and troughs.
>Similarly the ADC output consists of sharp periodic spikes. My SLCK
>and CS signals don't look very clean on the scope. How can I improve
>the quality of these if I need to drive the ADC from the FPGA? What
>else should I consider to resolve this problem?

What does your signal looks like if you remove the probe. And put the adc
inside a shielded box..?

Other than that:
 * Trace lengths equally long?
 * Trace impedance
 * Termination resistors
 * Analog/Digital seperation for power and groundplane
 * Shielding  (possible even a shielding barrier between analog & digital)
 * Radiated energy? wire=antenna..
 * Enough power, ripple issues
 * Faulty component

Have you checked the power supplies and ground to the ADC?  This
sounds like a weird problem, so look at something odd in the
design.  I doubt that the CS and SCLK signals could cause the
ADC to act like this unless there is something screwed up in how
the ADC is hooked up.

Also...
   - your are using good grounding on the scope probe, right?
   - if you're using a digital scope, you're sampling at a high enough
     frequency to avoid aliasing?  I've seen truly odd waveforms from
     digital scopes if they're used improperly.

Good luck!

John Providenza


m_oylulan@hotmail.com wrote:
> I am not sure if anyone is still reading this, but I've tested
> the ADC with worrying results. When I apply a sine wave to the input
> of the ADC with no SCLK or CS signal from FPGA, I can clearly
> see the sinewave on an oscilloscope. When I then use the FPGA
> to drive the CS and SCLK pins, the pure sine wave input to the
> ADC is no longer visible on the scope. What I see instead is what
> appears to be a bouncing noisy signal with sharp peaks and troughs.
> Similarly the ADC output consists of sharp periodic spikes. My SLCK
> and CS signals don't look very clean on the scope. How can I improve
> the quality of these if I need to drive the ADC from the FPGA? What
> else should I consider to resolve this problem?
> 
> Thanks,
> 
> Mees