How do I use the DDS core in a verilog flow?

I am new to using Xilinx cores. My intention is to use the DDS core,
for which I was able to generate a number of files using coregen. It
appears that only the "padded" EDIF can be run through the backend
stages. My question - as naive as it is - is what do you instantiate in
a higher level verilog module in order to implement the design?

xilinx_user wrote:
> I am new to using Xilinx cores. My intention is to use the DDS core,
> for which I was able to generate a number of files using coregen. It
> appears that only the "padded" EDIF can be run through the backend
> stages. My question - as naive as it is - is what do you instantiate in
> a higher level verilog module in order to implement the design?
> 
take a look at core_name.veo (core_name.vho for vhdl) vit a text editor, 
these files have instantiation template for your core (all the 
param/generics and ports)

(replace core_name with your actual core name)
have fun,
Aurash

Aurelian Lazarut wrote:
> xilinx_user wrote:
> > I am new to using Xilinx cores. My intention is to use the DDS core,
> > for which I was able to generate a number of files using coregen. It
> > appears that only the "padded" EDIF can be run through the backend
> > stages. My question - as naive as it is - is what do you instantiate in
> > a higher level verilog module in order to implement the design?
> >
> take a look at core_name.veo (core_name.vho for vhdl) vit a text editor,
> these files have instantiation template for your core (all the
> param/generics and ports)
>
> (replace core_name with your actual core name)
> have fun,
> Aurash

I tried that. The problem is that when you instantiate a verilog module
it will implicitly refer to a ".V" file, which is the simulation model.
It appears that only the EDIF file can be used for
synthesis/place&route.

What am I misinterpreting?

just rename, or move these *.v files (behavioral models) from your way, 
and make sure the edifs are into the working directory, and should work.
Aurash

xilinx_user wrote:

>Aurelian Lazarut wrote:
>  
>
>>xilinx_user wrote:
>>    
>>
>>>I am new to using Xilinx cores. My intention is to use the DDS core,
>>>for which I was able to generate a number of files using coregen. It
>>>appears that only the "padded" EDIF can be run through the backend
>>>stages. My question - as naive as it is - is what do you instantiate in
>>>a higher level verilog module in order to implement the design?
>>>
>>>      
>>>
>>take a look at core_name.veo (core_name.vho for vhdl) vit a text editor,
>>these files have instantiation template for your core (all the
>>param/generics and ports)
>>
>>(replace core_name with your actual core name)
>>have fun,
>>Aurash
>>    
>>
>
>I tried that. The problem is that when you instantiate a verilog module
>it will implicitly refer to a ".V" file, which is the simulation model.
>It appears that only the EDIF file can be used for
>synthesis/place&route.
>
>What am I misinterpreting?
>
>  
>


-- 
 __
/ /\/\ Aurelian Lazarut
\ \  / System Verification Engineer
/ /  \ Xilinx Ireland
\_\/\/
 
phone:	353 01 4032639
fax:	353 01 4640324
    
     

xilinx_user skrev:

> Aurelian Lazarut wrote:
> > xilinx_user wrote:
> > > I am new to using Xilinx cores. My intention is to use the DDS core,
> > > for which I was able to generate a number of files using coregen. It
> > > appears that only the "padded" EDIF can be run through the backend
> > > stages. My question - as naive as it is - is what do you instantiate in
> > > a higher level verilog module in order to implement the design?
> > >
> > take a look at core_name.veo (core_name.vho for vhdl) vit a text editor,
> > these files have instantiation template for your core (all the
> > param/generics and ports)
> >
> > (replace core_name with your actual core name)
> > have fun,
> > Aurash
>
> I tried that. The problem is that when you instantiate a verilog module
> it will implicitly refer to a ".V" file, which is the simulation model.
> It appears that only the EDIF file can be used for
> synthesis/place&route.
>
> What am I misinterpreting?

if I use coregen to generate a, for example, a memory block called
"ram2kx8"  I get
from coregen:

ram2kx8.v: that is the wrapper you need to include in you synthesis and
simulation.
ram2kx8.veo: that is a file with an example of how to instatiate the
module (cut-n-paste from this file as needed)
ram2kx8.edn: the edif file need to be in a place where the place and
route toold can find it

-Lasse

Aurelian Lazarut wrote:
> just rename, or move these *.v files (behavioral models) from your way,
> and make sure the edifs are into the working directory, and should work.
> Aurash
> / /\/\ Aurelian Lazarut
> \ \  / System Verification Engineer
> / /  \ Xilinx Ireland
> phone:	353 01 4032639
> fax:	353 01 4640324

I am still having trouble.

I have a working directory called "exhaust." In this directory I have
the following:

xyz.v
sine_dds.edn

File xyz.v contains the following:

module xyz(CLK,WE,SCLK,WE,A,SINE);
input CLK,WE,SCLK;
input [4:0] A;
output [20:0] SINE;



sine_dds sine_new(
	.DATA(DATA),
	.WE(WE),
	.A(A),
	.CLK(CLK),
	.CE(CE),
	.SCLR(SCLR),
	.SINE(SINE));
endmodule

When I try to synthesize xyz.v, I get the following error message:

ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
'sine_dds'

line 10 is "sine_dds sine_new("


I am lost, and I do not know what I am doing wrong. By the way I am
using webpack 8.1

Art

xilinx_user skrev:

> Aurelian Lazarut wrote:
> > just rename, or move these *.v files (behavioral models) from your way,
> > and make sure the edifs are into the working directory, and should work.
> > Aurash
> > / /\/\ Aurelian Lazarut
> > \ \  / System Verification Engineer
> > / /  \ Xilinx Ireland
> > phone:	353 01 4032639
> > fax:	353 01 4640324
>
> I am still having trouble.
>
> I have a working directory called "exhaust." In this directory I have
> the following:
>
> xyz.v
> sine_dds.edn
>
> File xyz.v contains the following:
>
> module xyz(CLK,WE,SCLK,WE,A,SINE);
> input CLK,WE,SCLK;
> input [4:0] A;
> output [20:0] SINE;
>
>
>
> sine_dds sine_new(
> 	.DATA(DATA),
> 	.WE(WE),
> 	.A(A),
> 	.CLK(CLK),
> 	.CE(CE),
> 	.SCLR(SCLR),
> 	.SINE(SINE));
> endmodule
>
> When I try to synthesize xyz.v, I get the following error message:
>
> ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> 'sine_dds'
>
> line 10 is "sine_dds sine_new("
>
>
> I am lost, and I do not know what I am doing wrong. By the way I am
> using webpack 8.1
>
> Art

Coregen should also have generated a sine_dds.v file, add that  to the
project

-Lasse

langwadt@ieee.org wrote:
> xilinx_user skrev:
>
> > Aurelian Lazarut wrote:
> > > just rename, or move these *.v files (behavioral models) from your way,
> > > and make sure the edifs are into the working directory, and should work.
> > > Aurash
> > > / /\/\ Aurelian Lazarut
> > > \ \  / System Verification Engineer
> > > / /  \ Xilinx Ireland
> > > phone:	353 01 4032639
> > > fax:	353 01 4640324
> >
> > I am still having trouble.
> >
> > I have a working directory called "exhaust." In this directory I have
> > the following:
> >
> > xyz.v
> > sine_dds.edn
> >
> > File xyz.v contains the following:
> >
> > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > input CLK,WE,SCLK;
> > input [4:0] A;
> > output [20:0] SINE;
> >
> >
> >
> > sine_dds sine_new(
> > 	.DATA(DATA),
> > 	.WE(WE),
> > 	.A(A),
> > 	.CLK(CLK),
> > 	.CE(CE),
> > 	.SCLR(SCLR),
> > 	.SINE(SINE));
> > endmodule
> >
> > When I try to synthesize xyz.v, I get the following error message:
> >
> > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > 'sine_dds'
> >
> > line 10 is "sine_dds sine_new("
> >
> >
> > I am lost, and I do not know what I am doing wrong. By the way I am
> > using webpack 8.1
> >
> > Art
>
> Coregen should also have generated a sine_dds.v file, add that  to the
> project
>
> -Lasse


sine_dds.v is the simulation file. From what I understand it cannot be
used for sythesis - only the edif file. Besides Aurelian Lazarut
already stated that I need to remove these from the working direcotyr.
It would appear something else is going on.

xilinx_user skrev:

> langwadt@ieee.org wrote:
> > xilinx_user skrev:
> >
> > > Aurelian Lazarut wrote:
> > > > just rename, or move these *.v files (behavioral models) from your way,
> > > > and make sure the edifs are into the working directory, and should work.
> > > > Aurash
> > > > / /\/\ Aurelian Lazarut
> > > > \ \  / System Verification Engineer
> > > > / /  \ Xilinx Ireland
> > > > phone:	353 01 4032639
> > > > fax:	353 01 4640324
> > >
> > > I am still having trouble.
> > >
> > > I have a working directory called "exhaust." In this directory I have
> > > the following:
> > >
> > > xyz.v
> > > sine_dds.edn
> > >
> > > File xyz.v contains the following:
> > >
> > > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > > input CLK,WE,SCLK;
> > > input [4:0] A;
> > > output [20:0] SINE;
> > >
> > >
> > >
> > > sine_dds sine_new(
> > > 	.DATA(DATA),
> > > 	.WE(WE),
> > > 	.A(A),
> > > 	.CLK(CLK),
> > > 	.CE(CE),
> > > 	.SCLR(SCLR),
> > > 	.SINE(SINE));
> > > endmodule
> > >
> > > When I try to synthesize xyz.v, I get the following error message:
> > >
> > > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > > 'sine_dds'
> > >
> > > line 10 is "sine_dds sine_new("
> > >
> > >
> > > I am lost, and I do not know what I am doing wrong. By the way I am
> > > using webpack 8.1
> > >
> > > Art
> >
> > Coregen should also have generated a sine_dds.v file, add that  to the
> > project
> >
> > -Lasse
>
>
> sine_dds.v is the simulation file. From what I understand it cannot be
> used for sythesis - only the edif file. Besides Aurelian Lazarut
> already stated that I need to remove these from the working direcotyr.
> It would appear something else is going on.

sine_dds.v has the module definition for synthesis and enclosed in
translate_off/translate_on the stuff for simulation.

but if you don't want to listen ... ;)

-Lasse

langwadt@ieee.org wrote:
> xilinx_user skrev:
>
> > langwadt@ieee.org wrote:
> > > xilinx_user skrev:
> > >
> > > > Aurelian Lazarut wrote:
> > > > > just rename, or move these *.v files (behavioral models) from your way,
> > > > > and make sure the edifs are into the working directory, and should work.
> > > > > Aurash
> > > > > / /\/\ Aurelian Lazarut
> > > > > \ \  / System Verification Engineer
> > > > > / /  \ Xilinx Ireland
> > > > > phone:	353 01 4032639
> > > > > fax:	353 01 4640324
> > > >
> > > > I am still having trouble.
> > > >
> > > > I have a working directory called "exhaust." In this directory I have
> > > > the following:
> > > >
> > > > xyz.v
> > > > sine_dds.edn
> > > >
> > > > File xyz.v contains the following:
> > > >
> > > > module xyz(CLK,WE,SCLK,WE,A,SINE);
> > > > input CLK,WE,SCLK;
> > > > input [4:0] A;
> > > > output [20:0] SINE;
> > > >
> > > >
> > > >
> > > > sine_dds sine_new(
> > > > 	.DATA(DATA),
> > > > 	.WE(WE),
> > > > 	.A(A),
> > > > 	.CLK(CLK),
> > > > 	.CE(CE),
> > > > 	.SCLR(SCLR),
> > > > 	.SINE(SINE));
> > > > endmodule
> > > >
> > > > When I try to synthesize xyz.v, I get the following error message:
> > > >
> > > > ERROR:HDLCompilers:87 - "xyz.v" line 10 Could not find module/primitive
> > > > 'sine_dds'
> > > >
> > > > line 10 is "sine_dds sine_new("
> > > >
> > > >
> > > > I am lost, and I do not know what I am doing wrong. By the way I am
> > > > using webpack 8.1
> > > >
> > > > Art
> > >
> > > Coregen should also have generated a sine_dds.v file, add that  to the
> > > project
> > >
> > > -Lasse
> >
> >
> > sine_dds.v is the simulation file. From what I understand it cannot be
> > used for sythesis - only the edif file. Besides Aurelian Lazarut
> > already stated that I need to remove these from the working direcotyr.
> > It would appear something else is going on.
>
> sine_dds.v has the module definition for synthesis and enclosed in
> translate_off/translate_on the stuff for simulation.
>
> but if you don't want to listen ... ;)
>
> -Lasse

Sir,

Your comment: "but if you don't want to listen ... ;) " is not helpful.
I originally had the .v file in  the directory and it did not work.
Aurelian Lazarut, who is a System Verification Engineer
for Xilinx Ireland said to remove them and make sure all the edif files
are in the working directory. As he works for Xilinx I am inclined to
take his word.

Just for the record, the comment in the .v file is: "This file cannot
be synthesized and should only be used with supported simulation
tools."

I am sorry you take offense but I am losing time in getting the answer
I need.