Hi, Can anyone point me to the spec. for the maximum clock frequency for the CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? Ta, Syms. Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
IDELAY clock spec. in Xilinx V4
Started by ●June 13, 2006
Reply by ●June 13, 20062006-06-13
Symon, IDELAY doesn't have a CLKDIV pin, IDELAYCTRL has nothing to do with CLKDIV (assuming you are talking about ISERDES , CLKDIV) IDELAYCTRL is more like a "servo loop" which calibrates the tap delay for the delay element close to 75ps (using the 200MHz as a ref) to compensate for voltage temperature variation. that's why if you are going to use IDELAY element you have to instantiate the IDELAYCTRL in the same IO bank. as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more flexibility for the user) however if you were reffering to ISERDES clkdiv, then this is the serial clock divided by the number of stages in the deserializer (for SDR) , in other words the frequency for the paralell de-serialized data, so it's a function of serial frequency, stages into the de-serializer and SDR/DDR. the clk div is "fabricated" by the means of BUFR (regional buffers) where you can setup the div factor. Aurash Symon wrote:>Hi, >Can anyone point me to the spec. for the maximum clock frequency for the >CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need >a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? >Ta, Syms. > > > >Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php > >-- __ / /\/\ Aurelian Lazarut \ \ / System Verification Engineer / / \ Xilinx Ireland \_\/\/ phone: 353 01 4032639 fax: 353 01 4640324
Reply by ●June 13, 20062006-06-13
Let me just add that this wider range of the reference clock (180 to 220 MHz) also applies to Virtex-4. The original tight specification and any warnings about jitter on that clock were overly conservative. We have run extensive tests... Peter Alfke =================== Aurelian Lazarut wrote:> > > as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it > can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more > flexibility for the user) > >
Reply by ●June 13, 20062006-06-13
Symon, The Ref Clock may be supplied from any +/- 10% 200 MHz source, including the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need to be concerned with the jitter from the CLKFX, as the analog locked loop which controls the delay is effectively a PLL which filters out the high frequency jitter components (jitter on Refclk is attenuated when transfered to the data lines). It is not our intent to require a separate oscillator for this function, one should be able to make good use of the clocks that are already part of your design. Initially we did not mention use of the DCM as a source of clock for the IDELAY, as it took some time to finish the characterization of the jitter attenuation of the analog loop used. Austin Symon wrote:> Hi, > Can anyone point me to the spec. for the maximum clock frequency for the > CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks need > a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? > Ta, Syms. > > > > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
Reply by ●June 13, 20062006-06-13
Hi Aurash, Thanks for your reply! I should perhaps refine my question! Looking at a freshly downloaded UG070, the V4 user guide, Figure 7-1: ILOGIC Block Diagram, I can see a pin called CLKDIV which connects via CLKDIVINV to the block IDELAY, pin CLK. Where is the specification for the maximum frequency of this clock? BTW, I'm not using ISERDES. Thanks again, Syms. "Aurelian Lazarut" <aurash@xilinx.com> wrote in message news:e6mp3t$6j21@cliff.xsj.xilinx.com...> Symon, > > IDELAY doesn't have a CLKDIV pin, IDELAYCTRL has nothing to do with CLKDIV > (assuming you are talking about ISERDES , CLKDIV) > IDELAYCTRL is more like a "servo loop" which calibrates the tap delay for > the delay element close to 75ps (using the 200MHz as a ref) to compensate > for voltage temperature variation. > that's why if you are going to use IDELAY element you have to instantiate > the IDELAYCTRL in the same IO bank. > > as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it can > be from 180Mhz to 220Mhz, so the delay/tap will vary. (more flexibility > for the user) > > however if you were reffering to ISERDES clkdiv, then this is the serial > clock divided by the number of stages in the deserializer (for SDR) , in > other words the frequency for the paralell de-serialized data, so it's a > function of serial frequency, stages into the de-serializer and SDR/DDR. > the clk div is "fabricated" by the means of BUFR (regional buffers) where > you can setup the div factor. > > Aurash >
Reply by ●June 13, 20062006-06-13
Hi Peter, Thanks for that, that gives me a little more flexibility. Best, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:1150218602.914281.192260@g10g2000cwb.googlegroups.com...> Let me just add that this wider range of the reference clock (180 to > 220 MHz) also applies to Virtex-4. The original tight specification and > any warnings about jitter on that clock were overly conservative. We > have run extensive tests... > Peter Alfke > =================== > Aurelian Lazarut wrote: >> > >> as a difference in virtex5 this REF_CLK which feeds the IDELAYCRTL it >> can be from 180Mhz to 220Mhz, so the delay/tap will vary. (more >> flexibility for the user) >> >> >Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
Reply by ●June 13, 20062006-06-13
Hi Austin, Thanks for that, you've confirmed what I thought the datasheet told me! But part of my question remains. Where do I find the specification for the maximum clock frequency on the IDELAY block remains? In other words, if I want to use the IDELAY block (Figure 7-11: IDELAY Primitive in UG070) in Variable delay mode (IOBDELAY_TYPE = VARIABLE), how fast can I clock it? Regards, Syms. "Austin Lesea" <austin@xilinx.com> wrote in message news:e6ms5c$lji1@xco-news.xilinx.com...> Symon, > > The Ref Clock may be supplied from any +/- 10% 200 MHz source, including > the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, > D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need > to be concerned with the jitter from the CLKFX, as the analog locked > loop which controls the delay is effectively a PLL which filters out the > high frequency jitter components (jitter on Refclk is attenuated when > transfered to the data lines). > > It is not our intent to require a separate oscillator for this function, > one should be able to make good use of the clocks that are already part > of your design. > > Initially we did not mention use of the DCM as a source of clock for the > IDELAY, as it took some time to finish the characterization of the > jitter attenuation of the analog loop used. > > Austin > > Symon wrote: >> Hi, >> Can anyone point me to the spec. for the maximum clock frequency for the >> CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks >> need >> a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? >> Ta, Syms. >> >> >> >> Inviato da X-Privat.Org - Registrazione gratuita >> http://www.x-privat.org/join.phpInviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
Reply by ●June 13, 20062006-06-13
Symon, OK, I looked for it, and I can't find it. This clock is used for the control of the IDELAY block, and our usual goal is to have control stuff be able to run at the fabric speed (~400 MHz), but I will go find out what it actually is. Sometimes (rarely) these sorts of interfaces can not run at the full fabric speed. Austin Symon wrote:> Hi Austin, > Thanks for that, you've confirmed what I thought the datasheet told me! But > part of my question remains. > Where do I find the specification for the maximum clock frequency on the > IDELAY block remains? In other words, if I want to use the IDELAY block > (Figure 7-11: IDELAY Primitive in UG070) in Variable delay mode > (IOBDELAY_TYPE = VARIABLE), how fast can I clock it? > Regards, Syms. > > "Austin Lesea" <austin@xilinx.com> wrote in message > news:e6ms5c$lji1@xco-news.xilinx.com... >> Symon, >> >> The Ref Clock may be supplied from any +/- 10% 200 MHz source, including >> the DCM CLKFX output. For example, if there is a 66 MHz clock, a M=3, >> D=1 will provide you with a ~ 200 MHz output on CLKFX. There is no need >> to be concerned with the jitter from the CLKFX, as the analog locked >> loop which controls the delay is effectively a PLL which filters out the >> high frequency jitter components (jitter on Refclk is attenuated when >> transfered to the data lines). >> >> It is not our intent to require a separate oscillator for this function, >> one should be able to make good use of the clocks that are already part >> of your design. >> >> Initially we did not mention use of the DCM as a source of clock for the >> IDELAY, as it took some time to finish the characterization of the >> jitter attenuation of the analog loop used. >> >> Austin >> >> Symon wrote: >>> Hi, >>> Can anyone point me to the spec. for the maximum clock frequency for the >>> CLKDIV pin of the IDELAY block in Virtex 4? I see the IDELAYCTRL blocks >>> need >>> a 200MHz REFCLK, +/- 10MHz, do I need to use this for the CLKDIV pin? >>> Ta, Syms. >>> >>> >>> >>> Inviato da X-Privat.Org - Registrazione gratuita >>> http://www.x-privat.org/join.php > > > > Inviato da X-Privat.Org - Registrazione gratuita http://www.x-privat.org/join.php
Reply by ●June 13, 20062006-06-13
I turned over some stones: The stepping of the IDELAY taps can definitely be done at the IDELAY output clock rate, or at 250 MHz, and probably even faster. It's just a counter driving a decoder, so I could imagine that it is even much faster. But 250 MHz is no problem... Peter Alfke, Xilinx Applications ================= Austin Lesea wrote:> Symon, > > OK, I looked for it, and I can't find it. > > This clock is used for the control of the IDELAY block, and our usual > goal is to have control stuff be able to run at the fabric speed (~400 > MHz), but I will go find out what it actually is. Sometimes (rarely) > these sorts of interfaces can not run at the full fabric speed. > > Austin > >
Reply by ●June 14, 20062006-06-14
Hi Guys, OK, many thanks for that, it'd be cool if you could find out the actual speed. Thanks again, Syms. "Peter Alfke" <peter@xilinx.com> wrote in message news:1150229559.983503.310330@p79g2000cwp.googlegroups.com...>I turned over some stones: > The stepping of the IDELAY taps can definitely be done at the IDELAY > output clock rate, or at 250 MHz, and probably even faster. It's just a > counter driving a decoder, so I could imagine that it is even much > faster. But 250 MHz is no problem... > Peter Alfke, Xilinx Applications > ================= > Austin Lesea wrote: >> Symon, >> >> OK, I looked for it, and I can't find it. >> >> This clock is used for the control of the IDELAY block, and our usual >> goal is to have control stuff be able to run at the fabric speed (~400 >> MHz), but I will go find out what it actually is. Sometimes (rarely) >> these sorts of interfaces can not run at the full fabric speed. >> >> Austin >> >> >
