I am trying to connect to the XMDSTUB on the MicroBlaze (MB) board using ver 8.1.03i EDK (i.e., I have 8.1i EDK and have upgraded to SP3). I am building a basic MicroBlaze system: a MicroBlaze (soft-core) processor, memory, and a UART, as in the following "lab" document: http://www.eecg.toronto.edu/~pc/courses/edk/modules/6.1/Lab1.v1.1.pdf This works for me when I use ver (approx) 6.1, but not when I use ver 8.1.03i -- on different computers, but I doubt that is the problem. I moved the same MB, cables, power-bricks, cords, etc., between the computers. Using ver 8.1.03i, I try to follow the directions in that document as best I can given that the user interface has changed greatly. I use the simple counter loop program from the lab. I generate the Bitstream, generate the libraries, download the bitstream to the MB board successfully, and run XMD. I get the following: ----------------------------------------------------------------- Xilinx Microprocessor Debug (XMD) Engine Xilinx EDK 8.1.02 Build EDK_I.20.4 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. XMD% Loading XMP File.. Processor(s) in System :: Microblaze(0) : microblaze_0 Address Map for Processor microblaze_0 (0x00000000-0x0000ffff) dlmb_cntlr dlmb (0x00000000-0x0000ffff) ilmb_cntlr ilmb (0x40600000-0x4060ffff) RS232 mb_opb (0x41400000-0x4140ffff) debug_module mb_opb Connecting to cable (Parallel Port - LPT1). Checking cable driver. Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h. ECP base address = 0778h. ECP hardware is detected. Cable connection established. Connecting to cable (Parallel Port - LPT1) in ECP mode. Checking cable driver. Driver xpc4drvr.sys version = 1.0.4.0. LPT base address = 0378h. Cable Type = 1, Revision = 3. Setting cable speed to 5 MHz. Cable connection established. JTAG chain configuration -------------------------------------------------- Device ID Code IR Length Part Name 1 0a001093 8 System_ACE 2 01038093 6 XC2V2000 Assuming, Device No: 2 contains the MicroBlaze system Connected to the JTAG MicroProcessor Debug Module (MDM) No of processors = 0 JTAG Uart ReadByte timeout JTAG Uart ReadByte timeout Unable to sync with stub on board No response to Debug_SYS_Rst signal (System Reset) Verify if FPGA is configured correctly or XMDSTUB is running on Board. XMD% ----------------------------------------------------------------- I tried it with both "Enable MicroBlaze Debug Module Interface" and without -- found on the "Debug" tab of the dialog box obtained when you double-click on the microblaze_0 instance in the System Assembly Bus Interface View. I also tried it with the old .xbd file: Xilinx_Multimedia_v2_1_0.xbd - the new file is Xilinx_Multimedia_v2_2_0.xbd at C:\EDK\board\Xilinx\boards\Xilinx_Multimedia\data Also I fixed a pin mistake in the data/system.ucf file: D10 is the pin for user SW0, not for the sys_rst_pin. AH7 as the sys_rst_pin worked when I did this in ver 6. I changed it to AH7 so that it gets as far as the output above; otherwise it doesn't even get that far. Can anyone help me with this? Thanks.
Xilinx MicroBlaze and Multimedia Demo. board: Debugging: 8.1.03i EDK - Unable to sync with stub on board
Started by ●June 15, 2006
Reply by ●June 16, 20062006-06-16
Also, I remember to compile the software and update the bitstream before downloading. james7uw@yahoo.ca wrote:> I am trying to connect to the XMDSTUB on the MicroBlaze (MB) > board using ver 8.1.03i EDK (i.e., I have 8.1i EDK and have > upgraded to SP3). > > I am building a basic MicroBlaze system: a MicroBlaze (soft-core) > processor, memory, and a UART, as in the following "lab" > document: > http://www.eecg.toronto.edu/~pc/courses/edk/modules/6.1/Lab1.v1.1.pdf > > This works for me when I use ver (approx) 6.1, but not when I use > ver 8.1.03i -- on different computers, but I doubt that is the > problem. I moved the same MB, cables, power-bricks, cords, etc., > between the computers. > > Using ver 8.1.03i, I try to follow the directions in that > document as best I can given that the user interface has changed > greatly. > > I use the simple counter loop program from the lab. I generate > the Bitstream, generate the libraries, download the bitstream to > the MB board successfully, and run XMD. I get the following: > > ----------------------------------------------------------------- > Xilinx Microprocessor Debug (XMD) Engine > Xilinx EDK 8.1.02 Build EDK_I.20.4 > Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. > > XMD% > Loading XMP File.. > Processor(s) in System :: > > Microblaze(0) : microblaze_0 > Address Map for Processor microblaze_0 > (0x00000000-0x0000ffff) dlmb_cntlr dlmb > (0x00000000-0x0000ffff) ilmb_cntlr ilmb > (0x40600000-0x4060ffff) RS232 mb_opb > (0x41400000-0x4140ffff) debug_module mb_opb > > Connecting to cable (Parallel Port - LPT1). > Checking cable driver. > Driver windrvr6.sys version = 7.0.0.0. LPT base address = 0378h. > ECP base address = 0778h. > ECP hardware is detected. > Cable connection established. > Connecting to cable (Parallel Port - LPT1) in ECP mode. > Checking cable driver. > Driver xpc4drvr.sys version = 1.0.4.0. LPT base address = 0378h. > Cable Type = 1, Revision = 3. > Setting cable speed to 5 MHz. > Cable connection established. > > JTAG chain configuration > -------------------------------------------------- > Device ID Code IR Length Part Name > 1 0a001093 8 System_ACE > 2 01038093 6 XC2V2000 > Assuming, Device No: 2 contains the MicroBlaze system > Connected to the JTAG MicroProcessor Debug Module (MDM) > No of processors = 0 > > JTAG Uart ReadByte timeout > JTAG Uart ReadByte timeout > Unable to sync with stub on board > No response to Debug_SYS_Rst signal (System Reset) > Verify if FPGA is configured correctly or XMDSTUB is running on > Board. > > XMD% > ----------------------------------------------------------------- > > I tried it with both "Enable MicroBlaze Debug Module Interface" > and without -- found on the "Debug" tab of the dialog box > obtained when you double-click on the microblaze_0 instance in > the System Assembly Bus Interface View. > > I also tried it with the old .xbd file: > Xilinx_Multimedia_v2_1_0.xbd - the new file is > Xilinx_Multimedia_v2_2_0.xbd at > C:\EDK\board\Xilinx\boards\Xilinx_Multimedia\data > > Also I fixed a pin mistake in the data/system.ucf file: D10 is > the pin for user SW0, not for the sys_rst_pin. AH7 as the > sys_rst_pin worked when I did this in ver 6. I changed it to AH7 > so that it gets as far as the output above; otherwise it doesn't > even get that far. > > Can anyone help me with this? > > Thanks.
