The VHDL source and UCF file are at the bottom of this document. The error that I'm getting is: NCD was not produced. All logic was removed from design. This is usually due to having no input or output PAD connections in the design and no nets or symbols marked as 'SAVE'. You can either add PADs or 'SAVE' attributes to the design, or run 'map -u' to disable logic trimming in the mapper. I've got all my ports connected (see the UCF), and my logic seems right (it's just a sample from the Xilinx "Quick Start") ... what am I missing? I can get something simple working (like, OUTPUT(0) <= SWITCH1; -- as the whole body), but anything more complex generates this error. Any help would be greatly appreciated. Thank you! The VHDL: entity ffff is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end ffff; architecture Behavioral of ffff is signal count_int : std_logic_vector(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= count_int; end Behavioral; The UCF: NET "CLOCK" LOC = "C9" | IOSTANDARD = LVCMOS33; NET "CLOCK" PERIOD = 20.0ns HIGH 40%; NET "COUNT_OUT<0>" LOC = "F12" ; NET "COUNT_OUT<1>" LOC = "E12" ; NET "COUNT_OUT<2>" LOC = "E11" ; NET "COUNT_OUT<3>" LOC = "F11" ; NET "DIRECTION" LOC = "L13" ;
Xilinx ISE 8.1i Trouble
Started by ●June 20, 2006
Reply by ●June 20, 20062006-06-20
Try NET "COUNT_OUT[0]" LOC = "F12" ; NET "COUNT_OUT[1]" LOC = "E12" ; NET "COUNT_OUT[2]" LOC = "E11" ; NET "COUNT_OUT[3]" LOC = "F11" ; -girmann Alex wrote:> The VHDL source and UCF file are at the bottom of this document. > > The error that I'm getting is: > NCD was not produced. All logic was removed from design. This > is usually due to having no input or output PAD connections in the > design and > no nets or symbols marked as 'SAVE'. You can either add PADs or > 'SAVE' > attributes to the design, or run 'map -u' to disable logic trimming > in the > mapper. > > I've got all my ports connected (see the UCF), and my logic seems right > (it's just a sample from the Xilinx "Quick Start") ... what am I > missing? I can get something simple working (like, OUTPUT(0) <= > SWITCH1; -- as the whole body), but anything more complex generates > this error. > > Any help would be greatly appreciated. Thank you! > > > > The VHDL: > entity ffff is > Port ( CLOCK : in STD_LOGIC; > DIRECTION : in STD_LOGIC; > COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); > end ffff; > > architecture Behavioral of ffff is > signal count_int : std_logic_vector(3 downto 0) := "0000"; > begin > process (CLOCK) > begin > if CLOCK='1' and CLOCK'event then > if DIRECTION='1' then > count_int <= count_int + 1; > else > count_int <= count_int - 1; > end if; > end if; > end process; > COUNT_OUT <= count_int; > end Behavioral; > > > > The UCF: > NET "CLOCK" LOC = "C9" | IOSTANDARD = LVCMOS33; > NET "CLOCK" PERIOD = 20.0ns HIGH 40%; > > NET "COUNT_OUT<0>" LOC = "F12" ; > NET "COUNT_OUT<1>" LOC = "E12" ; > NET "COUNT_OUT<2>" LOC = "E11" ; > NET "COUNT_OUT<3>" LOC = "F11" ; > NET "DIRECTION" LOC = "L13" ;
Reply by ●June 20, 20062006-06-20
Same exact error, I'm afraid. Thanks for the try, though. girmann@gmail.com wrote:> Try > > NET "COUNT_OUT[0]" LOC = "F12" ; > NET "COUNT_OUT[1]" LOC = "E12" ; > NET "COUNT_OUT[2]" LOC = "E11" ; > NET "COUNT_OUT[3]" LOC = "F11" ; > > -girmann > > Alex wrote: > > The VHDL source and UCF file are at the bottom of this document. > > > > The error that I'm getting is: > > NCD was not produced. All logic was removed from design. This > > is usually due to having no input or output PAD connections in the > > design and > > no nets or symbols marked as 'SAVE'. You can either add PADs or > > 'SAVE' > > attributes to the design, or run 'map -u' to disable logic trimming > > in the > > mapper. > > > > I've got all my ports connected (see the UCF), and my logic seems right > > (it's just a sample from the Xilinx "Quick Start") ... what am I > > missing? I can get something simple working (like, OUTPUT(0) <= > > SWITCH1; -- as the whole body), but anything more complex generates > > this error. > > > > Any help would be greatly appreciated. Thank you! > > > > > > > > The VHDL: > > entity ffff is > > Port ( CLOCK : in STD_LOGIC; > > DIRECTION : in STD_LOGIC; > > COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); > > end ffff; > > > > architecture Behavioral of ffff is > > signal count_int : std_logic_vector(3 downto 0) := "0000"; > > begin > > process (CLOCK) > > begin > > if CLOCK='1' and CLOCK'event then > > if DIRECTION='1' then > > count_int <= count_int + 1; > > else > > count_int <= count_int - 1; > > end if; > > end if; > > end process; > > COUNT_OUT <= count_int; > > end Behavioral; > > > > > > > > The UCF: > > NET "CLOCK" LOC = "C9" | IOSTANDARD = LVCMOS33; > > NET "CLOCK" PERIOD = 20.0ns HIGH 40%; > > > > NET "COUNT_OUT<0>" LOC = "F12" ; > > NET "COUNT_OUT<1>" LOC = "E12" ; > > NET "COUNT_OUT<2>" LOC = "E11" ; > > NET "COUNT_OUT<3>" LOC = "F11" ; > > NET "DIRECTION" LOC = "L13" ;
Reply by ●June 20, 20062006-06-20
"Alex" <alexmchale@gmail.com> wrote in message news:1150811188.026823.5240@r2g2000cwb.googlegroups.com...> The error that I'm getting is: > NCD was not produced. All logic was removed from design. This > is usually due to having no input or output PAD connections in the > design and > no nets or symbols marked as 'SAVE'.What are you using to synthesize your design? If you are using XST (i.e. synthesis within ISE), make sure the "add I/O pads" option is checked in the GUI or passed on the command line. Otherwise the netlist created from synthesis will have no I/Os, and the mapper will throw away your design because it cannot affect the outside world... Cheers, -Ben-
Reply by ●June 20, 20062006-06-20
Alex wrote:> The VHDL source and UCF file are at the bottom of this document. > > The error that I'm getting is: > NCD was not produced. All logic was removed from design. This > is usually due to having no input or output PAD connections in the > design and > no nets or symbols marked as 'SAVE'. You can either add PADs or > 'SAVE' > attributes to the design, or run 'map -u' to disable logic trimming > in the > mapper. >Might I suggest you use use the numeric_std library? That works fine for me. From the par report file: Device Utilization Summary: Number of BUFGMUXs 1 out of 16 6% Number of External IOBs 6 out of 140 4% Number of LOCed IOBs 6 out of 6 100% Number of SLICEs 3 out of 1408 1% Using this file: library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity ffff is Port ( CLOCK : in STD_LOGIC; DIRECTION : in STD_LOGIC; COUNT_OUT : out STD_LOGIC_VECTOR (3 downto 0)); end ffff; architecture Behavioral of ffff is signal count_int : unsigned(3 downto 0) := "0000"; begin process (CLOCK) begin if CLOCK='1' and CLOCK'event then if DIRECTION='1' then count_int <= count_int + 1; else count_int <= count_int - 1; end if; end if; end process; COUNT_OUT <= std_logic_vector(count_int); end Behavioral;
Reply by ●June 20, 20062006-06-20
Yes, I am indeed using XST. Where is this "add I/O pads" option within ISE? Thanks! Alex McHale Ben Jones wrote:> "Alex" <alexmchale@gmail.com> wrote in message > news:1150811188.026823.5240@r2g2000cwb.googlegroups.com... > > > The error that I'm getting is: > > NCD was not produced. All logic was removed from design. This > > is usually due to having no input or output PAD connections in the > > design and > > no nets or symbols marked as 'SAVE'. > > What are you using to synthesize your design? > > If you are using XST (i.e. synthesis within ISE), make sure the "add I/O > pads" option is checked in the GUI or passed on the command line. Otherwise > the netlist created from synthesis will have no I/Os, and the mapper will > throw away your design because it cannot affect the outside world... > > Cheers, > > -Ben-
Reply by ●June 21, 20062006-06-21
"Alex" <alexmchale@gmail.com> wrote in message news:1150821352.453929.125790@c74g2000cwc.googlegroups.com...> Yes, I am indeed using XST. Where is this "add I/O pads" option within > ISE?Process Properties for XST | Xilinx Specific Options | Add I/O Buffers (should be checked). Cheers, -Ben-
Reply by ●June 21, 20062006-06-21
In that case, that did not solve the problem. That was already enabled. Any other thoughts? This is a complete road block for me in development. I just don't understand why this thing won't work with anything more complicated than directly wiring the switch to the LED. I can send a zip of my project to anyone willing to help. I'm using Xilinx 8.1i WebPACK, with the latest service pack. Thank you. Alex McHale Ben Jones wrote:> "Alex" <alexmchale@gmail.com> wrote in message > news:1150821352.453929.125790@c74g2000cwc.googlegroups.com... > > Yes, I am indeed using XST. Where is this "add I/O pads" option within > > ISE? > > Process Properties for XST | Xilinx Specific Options | Add I/O Buffers > (should be checked). > > Cheers, > > -Ben-
Reply by ●June 21, 20062006-06-21
Delving a bit deeper, I see that I am getting the following warnings before the final error. When I disable "Add I/O Buffers," I get these warnings on all of my lines. When it is enabled, I only get it for my CLOCK. While I'm sure my net list is correct, this must be a symptom of the issue that's preventing my vhdl to load. Any ideas? WARNING:NgdBuild:483 - Attribute "LOC" on "CLOCK" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute. WARNING:NgdBuild:483 - Attribute "IOSTANDARD" on "CLOCK" is on the wrong type of object. Please see the Constraints Guide for more information on this attribute.
Reply by ●June 21, 20062006-06-21
