Spartan-3 starter kit strange problem

Dear All,

I'm having a strange problem with my design that is driving me nuts...

I'm a newcomer to FPGA in general and to Xilinx tools in particular.
I'm using a
Spartan-3 starter kit board with a XC3S200FT256 FPGA and ISE & EDK 7.1.
My idea is to use the board as a controller for my hardware project.

I've started with one of EDK's reference designs (Spartan-3 MicroBlaze
Example Design) and change it to meet my specifications.

My present configuration in:
- microblaze
- 16 KB block RAM
- RS232 (OPB_UARTlite)
- 8 LEDs (OPB_GPIO)
- OPB_Timer
- 3 pushbuttons (OPB_GPIO)
- 8 DIP switches (OPB_GPIO)
- 1 custom IP core to drive the 7-segments LEDs on the board
- 1 custom IP core to drive a 2x16 LDC display
- 1 custom IP core to generate a 5 MHz ADC clock, by dividing the on
board 50 MHz clock, and to read 32 inputs from 4 8 bits ADCs.
- 1 32 bit GPIO instance, configured as all inputs.
- 1 32 bit GPIO instance, configured as all outputs.

The design compiles OK and I don't get any error message, at least as
far as I can tell.

Now, here is the strange part:

- If I connect all the modules to pins in the FPGA, using, of course,
the .UCF file, the code
does not run. It freezes after only a few lines. The first line of my
code is a printf statement,
and only a few characters are sent to the uart. After that, noting else
happens.

- If I comment, in the UCF file the, lines connecting the output GPIO
to the FPGA pins, the program runs as it is suppose to run (the input
GPIO is, for now, commented).

Note that this behavior does not depend on what the code does. It may
be
the complet code with the initiation and write/read instructions, or it
may be a simple "hello world" program. It doesn't matter.

I have read the documentation on the FPGA, to see if I was using somme
pins that I was not suppose to use, and I have also read the GPIO
specification, but could not find any hint on what the origine of my
problem is. What am I missing here? I must be doing a really stupid
error, but I can't find it. I'm sure this is not a problem with the
code, so it must be a problem in the design, but i'm not sure what kind
of hardware debugging techniques I should use in this case.

I'm posting the UCF below and I would appreciate any kind of help,
hint, suggestion, etc.

Tanks to all,

Jos=E9 Mariano

PS: Sorry for the lousy spell and the long post!!


############################################################################
## This system.ucf file is generated by Base System Builder based on
the
## settings in the selected Xilinx Board Definition file. Please add
other
## user constraints to this file based on customer design
specifications.
##
## Test version: ADC clock generated by IP and data read by IP
##
############################################################################

Net sys_clk_pin LOC=3DT9;
Net sys_rst_pin LOC=3Dl14;
## System level constraints
Net sys_clk_pin TNM_NET =3D sys_clk_pin;
TIMESPEC TS_sys_clk_pin =3D PERIOD sys_clk_pin 20000 ps;
Net sys_rst_pin TIG;

##########################################################
## FPGA pin constraints
##########################################################

## RS-232
Net fpga_0_RS232_RX_pin                     LOC=3Dt13;
Net fpga_0_RS232_TX_pin                     LOC=3Dr13;


## LEDs
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<0>      LOC=3Dk12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<1>      LOC=3Dp14;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<2>      LOC=3Dl12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<3>      LOC=3Dn14;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<4>      LOC=3Dp13;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<5>      LOC=3Dn12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<6>      LOC=3Dp12;
Net fpga_0_LEDs_8Bit_GPIO_d_out_pin<7>      LOC=3Dp11;


## Push Buttons
Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<0> LOC=3Dl13;
Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<1> LOC=3Dm14;
Net fpga_0_Push_Buttons_3Bit_GPIO_in_pin<2> LOC=3Dm13;


## DIP Switches pin constrains
Net DIP_Switches_8Bit_GPIO_in<0> LOC=3Dk13;
Net DIP_Switches_8Bit_GPIO_in<1> LOC=3Dk14;
Net DIP_Switches_8Bit_GPIO_in<2> LOC=3Dj13;
Net DIP_Switches_8Bit_GPIO_in<3> LOC=3Dj14;
Net DIP_Switches_8Bit_GPIO_in<4> LOC=3Dh13;
Net DIP_Switches_8Bit_GPIO_in<5> LOC=3Dh14;
Net DIP_Switches_8Bit_GPIO_in<6> LOC=3Dg12;
Net DIP_Switches_8Bit_GPIO_in<7> LOC=3Df12;


## 7 seg LED Display
Net digit<3> LOC=3Dd14;
Net digit<2> LOC=3Dg14;
Net digit<1> LOC=3Df14;
Net digit<0> LOC=3De13;
Net segment<7> LOC=3De14;
Net segment<6> LOC=3Dg13;
Net segment<5> LOC=3Dn15;
Net segment<4> LOC=3Dp15;
Net segment<3> LOC=3Dr16;
Net segment<2> LOC=3Df13;
Net segment<1> LOC=3Dn16;
Net segment<0> LOC=3Dp16;


## LCD
NET LCD_Data<7>     LOC=3Dn8;     ## 14
NET LCD_Data<6>     LOC=3Dn7;     ## 13
NET LCD_Data<5>     LOC=3Dt8;     ## 12
NET LCD_Data<4>     LOC=3Dr6;     ## 11
NET LCD_Data<3>     LOC=3Dt5;     ## 10
NET LCD_Data<2>     LOC=3Dr5;     ## 9
NET LCD_Data<1>     LOC=3Dc2;     ## 8
NET LCD_Data<0>     LOC=3Dc1;     ## 7
NET LCD_E           LOC=3Db1;     ## 6
NET LCD_RS          LOC=3Dm10;    ## 4
##NET LCD_RW        LOC=3Dm7;    ## gnd on the digital board


## GPIO - General purpose output
NET GPIO_Output_GPIO_d_out<0>       LOC=3Db8;     ## BW0->SwD1
NET GPIO_Output_GPIO_d_out<1>       LOC=3Db6;     ## BW1->SwD3
NET GPIO_Output_GPIO_d_out<2>       LOC=3Db7;     ## BW2->SwD4


## GPIO - General purpose input
##NET GPIO_Input_GPIO_in<0>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<1>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<2>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<3>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<4>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<5>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<6>       LOC=3Dxx;
##NET GPIO_Input_GPIO_in<7>       LOC=3Dxx;



## ADC's - INTEGRATOR IP
## ADC_0   -> In_Port[0:7]
## ADC_90  -> In_Port[8:15]
## ADC_180 -> In_Port[16:23]
## ADC_270 -> In_Port[24:31]
############################

NET fpga_INTEGRATOR_ENCODE_pin      LOC=3Da5;     ## ENCODE - ADC's Clock

NET fpga_INTEGRATOR_ADC0_pin<0>     LOC=3De10;
NET fpga_INTEGRATOR_ADC0_pin<1>       LOC=3Dc12;
NET fpga_INTEGRATOR_ADC0_pin<2>       LOC=3Dc11;
NET fpga_INTEGRATOR_ADC0_pin<3>       LOC=3Db14;
NET fpga_INTEGRATOR_ADC0_pin<4>       LOC=3Db13;
NET fpga_INTEGRATOR_ADC0_pin<5>       LOC=3Db12;
NET fpga_INTEGRATOR_ADC0_pin<6>       LOC=3Da10;
NET fpga_INTEGRATOR_ADC0_pin<7>       LOC=3Da9;

NET fpga_INTEGRATOR_ADC90_pin<0>      LOC=3De6;
NET fpga_INTEGRATOR_ADC90_pin<1>      LOC=3Dc5;
NET fpga_INTEGRATOR_ADC90_pin<2>      LOC=3Dc6;
NET fpga_INTEGRATOR_ADC90_pin<3>      LOC=3Dc7;
NET fpga_INTEGRATOR_ADC90_pin<4>      LOC=3Dc8;
NET fpga_INTEGRATOR_ADC90_pin<5>      LOC=3Dc9;
NET fpga_INTEGRATOR_ADC90_pin<6>      LOC=3Da3;
NET fpga_INTEGRATOR_ADC90_pin<7>      LOC=3Da4;

NET fpga_INTEGRATOR_ADC180_pin<0>      LOC=3Dc10;
NET fpga_INTEGRATOR_ADC180_pin<1>      LOC=3Dd11;
NET fpga_INTEGRATOR_ADC180_pin<2>      LOC=3Da13;
NET fpga_INTEGRATOR_ADC180_pin<3>      LOC=3Da12;
NET fpga_INTEGRATOR_ADC180_pin<4>      LOC=3Db11;
NET fpga_INTEGRATOR_ADC180_pin<5>      LOC=3Db10;
NET fpga_INTEGRATOR_ADC180_pin<6>      LOC=3Da8;
NET fpga_INTEGRATOR_ADC180_pin<7>      LOC=3Da7;

NET fpga_INTEGRATOR_ADC270_pin<0>       LOC=3Dd5;
NET fpga_INTEGRATOR_ADC270_pin<1>       LOC=3Dd6;
NET fpga_INTEGRATOR_ADC270_pin<2>       LOC=3De7;
NET fpga_INTEGRATOR_ADC270_pin<3>       LOC=3Dd7;
NET fpga_INTEGRATOR_ADC270_pin<4>       LOC=3Dd8;
NET fpga_INTEGRATOR_ADC270_pin<5>       LOC=3Dd10;
NET fpga_INTEGRATOR_ADC270_pin<6>       LOC=3Db4;
NET fpga_INTEGRATOR_ADC270_pin<7>       LOC=3Db5;

jmariano wrote:
> Dear All,
> 
<snip>>
> Now, here is the strange part:
> 
> - If I connect all the modules to pins in the FPGA, using, of course,
> the .UCF file, the code
> does not run. It freezes after only a few lines. The first line of my
> code is a printf statement,
> and only a few characters are sent to the uart. After that, noting else
> happens.
> 
> - If I comment, in the UCF file the, lines connecting the output GPIO
> to the FPGA pins, the program runs as it is suppose to run (the input
> GPIO is, for now, commented).
> 

That is strange. I'd check the following:
- make sure interrupts are disabled
- if you are using 'printf' and not 'xil_printf' then the stack space 
requirements will be high. Check your linker script to make sure you are 
allocating enough space on the stack.
- connect to the target using XMD, and see where exactly the processor 
is stalled. Correlate the PC back to the sources and see if you can spot 
the bug.
- try using the Virtual Platform tool for your design. In cases that it 
does work, it spots invalid memory accesses earlier..

/Siva

Hello Siva,

Tank you very much for your help. I managed to solve the problem with
the help Rob
Barris, who reply to the same message posted elsewhere. It turns out
that the origin of
the problem was the unconnected nets. After I connected all the nets to
pins on the FPGA,
the problem disappeared.

Regards

Mariano