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problem in simulating FFT core on ISE 7.1

Started by tamania June 26, 2006
hi
im using xilinx ISE 7.1i with modelsim XE 6.0 starter in verilog....i
have been trying to simulate FFT core on modelsim...also i have
downloaded "radix 2 fft core" from xilinx core generator examples on
xilinx site but failed to simulate it.the error msg in modelsim is as
under...


---------------------------------------------------------------------------------------------------------------
Loading
f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver.dcm_clock_lost
# Loading f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver.BUFG
# Loading work.my_radix2_xfft1024
# ** Error: (vsim-3033) my_radix2_xfft1024.v(135): Instantiation of
'XFFT_V3_1' failed. The design unit was not found.
#         Region: /design_top_tb_tf/uut/U3
#         Searched libraries:
#             f:\Modelsim\win32xoem/../xilinx/verilog/xilinxcorelib_ver
#             f:\Modelsim\win32xoem/../xilinx/verilog/unisims_ver
#             work
# Loading work.glbl
# Error loading design
# Error: Error loading design
#        Pausing macro execution
# MACRO ./design_top_tb_tf.fdo PAUSED at line 9
---------------------------------------------------------------------------------------------------------------

both ways same error comes at the same line ...i.e.."instantiation of
XFFT_V3 failed"....whether i generate the core through core generator
or download from site..
also i hv downloaded FIFO asynchronous core from core generator
examples but it is simulating perfectly...means there is some problem
with fft core..
if anyone can help me plz let me kno as soon as possible.
thanx alot

Hi am using FFT core (VHDL model) and simulated using modelsim-xilinx edition without any problem. Did you update your model sim simulator with latest updates ?

rgds bijoy